Adder including transistor having oxide semiconductor layer

• US 8,638,123 B2
• Filed: 05/16/2012
• Issued: 01/28/2014
• Est. Priority Date: 05/20/2011
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Ohnuki, Tatsuya
• Primary Examiner(s): Richardson, Jany
• Application Number:
  US13/472,733
• Publication Number:
  US 20120297221A1
• Time in Patent Office: 622 Days
• Field of Search: None
• US Class Current: 326/103
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 2207/4802 Special implementations
• CPC Class Codes: G06F 7/485 Adding; Subtracting G06F7/4833, G06F7/4836 take precedence
• CPC Class Codes: G06F 7/501 Half or full adders, i.e. basic adder cells for one denomination
• CPC Class Codes: G06G 7/14 for addition or subtraction of vector quantities G06G7/22 ; computing the average by addition; differential amplifiers H03F3/45
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H03K 21/10 comprising logic circuits
• CPC Class Codes: H03K 3/356008 ensuring a predetermined initial state when the supply voltage has been applied; storing the actual state when the supply voltage fails digital storage cells each combining volatile and non-volatile storage properties G11C14/00

Abstract

A circuit in which a storage function and an arithmetic function are combined is proposed by using a transistor with low off-state current for forming a storage element. When the transistor with low off-state current is used, electric charge can be held, for example, in a node or the like between a source or a drain of the transistor with low off-state current and a gate of another transistor. Thus, the node or the like between one of the source or the drain of the transistor with low off-state current and the gate of the another transistor can be used as a storage element. In addition, leakage current accompanied by the operation of an adder can be reduced considerably. Accordingly, a signal processing circuit consuming less power can be formed.

Claims

1. An adder comprising:

a sum circuit electrically connected to a first power supply line and a second power supply line;

a first input terminal electrically connected to the sum circuit;

a second input terminal electrically connected to the sum circuit;

a third input terminal electrically connected to the sum circuit; and

a first output terminal electrically connected to the sum circuit;

wherein the sum circuit comprises;

a first transistor, one of a source and a drain of the first transistor is electrically connected to the first power supply line and the other of the source and the drain of the first transistor is electrically connected to the second power supply line; and

a second transistor comprising a channel formation region comprising an oxide semiconductor layer, one of a source and a drain of the second transistor is electrically connected to the third input terminal and the other of the source and the drain of the second transistor is electrically connected to a gate of the first transistor, and

wherein the sum circuit is configured to output a high-potential signal from the first output terminal in accordance with an input of a high-potential signal to any one of the first input terminal, the second input terminal, and the third input terminal or high-potential signals to the first input terminal, the second input terminal, and the third input terminal.

2. The adder according to claim 1, further comprising:

a first potential supply controller, wherein the sum circuit is electrically connected to the first power supply line through the first potential supply controller, and

a second potential supply controller, wherein the sum circuit is electrically connected to the second power supply line through the second potential supply controller.

3. The adder according to claim 2,

wherein the first potential supply controller comprises a third transistor,

wherein one of a source and a drain of the third transistor is electrically connected to the sum circuit and the other of the source and the drain of the third transistor is electrically connected to the first power supply line,

wherein a gate of the third transistor is configured to be supplied with a clock signal,

wherein the second potential supply controller comprises a fourth transistor,

wherein one of a source and a drain of the fourth transistor is electrically connected to the sum circuit and the other of the source and the drain of the fourth transistor is electrically connected to the second power supply line, and

wherein a gate of the fourth transistor is configured to be supplied with the clock signal.

4. The adder according to claim 2,

wherein the first potential supply controller comprises a third transistor,

wherein one of a source and a drain of the third transistor is electrically connected to the sum circuit and the other of the source and the drain of the third transistor is electrically connected to the first power supply line,

wherein a gate of the third transistor is configured to be supplied with a clock signal,

wherein the second potential supply controller comprises a fourth transistor,

wherein one of a source and a drain of the fourth transistor is electrically connected to the sum circuit and the other of the source and the drain of the fourth transistor is electrically connected to the second power supply line, and

wherein a gate of the fourth transistor is configured to be supplied with an inverted clock signal.

5. The adder according to claim 1, wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

6. An adder comprising:

a sum circuit electrically connected to a first power supply line and a second power supply line;

a carry circuit electrically connected to the first power supply line and the second power supply line;

a first input terminal electrically connected to the sum circuit and the carry circuit;

a second input terminal electrically connected to the sum circuit and the carry circuit;

a third input terminal electrically connected to the sum circuit and the carry circuit;

a first output terminal electrically connected to the sum circuit; and

a second output terminal electrically connected to the carry circuit,

wherein each of the sum circuit and the carry circuit comprises;

a first transistor, one of a source and a drain of the first transistor is electrically connected to the first power supply line and the other of the source and the drain of the first transistor is electrically connected to the second power supply line; and

a second transistor comprising an oxide semiconductor layer, one of a source and a drain of the second transistor is electrically connected to the third input terminal and the other of the source and the drain of the second transistor is electrically connected to a gate of the first transistor,

wherein the sum circuit is configured to output a high-potential signal from the first output terminal in accordance with an input of a high-potential signal to any one of the first input terminal, the second input terminal, and the third input terminal or high-potential signals to the first input terminal, the second input terminal, and the third input terminal, and

wherein the carry circuit is configured to output a high-potential signal from the second output terminal in accordance with an input of high-potentials to any two or three of the first input terminal, the second input terminal, and the third input terminal.

7. The adder according to claim 6, wherein the second output terminal is electrically connected to the third input terminal.

8. The adder according to claim 6, further comprising:

a first potential supply controller, wherein the sum circuit is electrically connected to the first power supply line through the first potential supply controller, and

a second potential supply controller, wherein the sum circuit is electrically connected to the second power supply line through the second potential supply controller.

9. The adder according to claim 8,

wherein the first potential supply controller comprises a third transistor,

wherein one of a source and a drain of the third transistor is electrically connected to the sum circuit and the other of the source and the drain of the third transistor is electrically connected to the first power supply line,

wherein a gate of the third transistor is configured to be supplied with a clock signal,

wherein the second potential supply controller comprises a fourth transistor,

wherein one of a source and a drain of the fourth transistor is electrically connected to the sum circuit and the other of the source and the drain of the fourth transistor is electrically connected to the second power supply line, and

wherein a gate of the fourth transistor is configured to be supplied with the clock signal.

10. The adder according to claim 8,

wherein the first potential supply controller comprises a third transistor,

wherein one of a source and a drain of the third transistor is electrically connected to the sum circuit and the other of the source and the drain of the third transistor is electrically connected to the first power supply line,

wherein a gate of the third transistor is configured to be supplied with a clock signal,

wherein the second potential supply controller comprises a fourth transistor,

wherein one of a source and a drain of the fourth transistor is electrically connected to the sum circuit and the other of the source and the drain of the fourth transistor is electrically connected to the second power supply line, and

wherein a gate of the fourth transistor is configured to be supplied with an inverted clock signal.

11. The adder according to claim 6, further comprising:

a first potential supply controller, wherein the carry circuit is electrically connected to the first power supply line through the first potential supply controller, and

a second potential supply controller, wherein the carry circuit is electrically connected to the second power supply line through the second potential supply controller.

12. The adder according to claim 11,

wherein the first potential supply controller comprises a third transistor,

wherein one of a source and a drain of the third transistor is electrically connected to the carry circuit and the other of the source and the drain of the third transistor is electrically connected to the first power supply line,

wherein a gate of the third transistor is configured to be supplied with a clock signal,

wherein the second potential supply controller comprises a fourth transistor,

wherein one of a source and a drain of the fourth transistor is electrically connected to the carry circuit and the other of the source and the drain of the fourth transistor is electrically connected to the second power supply line, and

wherein a gate of the fourth transistor is configured to be supplied with the clock signal.

13. The adder according to claim 11,

wherein the first potential supply controller comprises a third transistor,

wherein one of a source and a drain of the third transistor is electrically connected to the carry circuit and the other of the source and the drain of the third transistor is electrically connected to the first power supply line,

wherein a gate of the third transistor is configured to be supplied with a clock signal,

wherein the second potential supply controller comprises a fourth transistor,

wherein one of a source and a drain of the fourth transistor is electrically connected to the carry circuit and the other of the source and the drain of the fourth transistor is electrically connected to the second power supply line, and

wherein a gate of the fourth transistor is configured to be supplied with an inverted clock signal.

14. The adder according to claim 6, wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

15. An adder comprising:

a carry circuit electrically connected to a first power supply line and a second power supply line;

a first input terminal electrically connected to the carry circuit;

a second input terminal electrically connected to the carry circuit;

a third input terminal electrically connected to the carry circuit; and

a first output terminal electrically connected to the carry circuit,

wherein the carry circuit comprises;

a first transistor, one of a source and a drain of the first transistor is electrically connected to the first power supply line and the other of the source and the drain of the first transistor is electrically connected to the second power supply line;

a second transistor comprising a channel formation region comprising an oxide semiconductor layer, one of a source and a drain of the second transistor is electrically connected to the third input terminal and the other of the source and the drain of the second transistor is electrically connected to a gate of the first transistor, and

wherein the carry circuit is configured to output a high-potential signal from the first output terminal in accordance with an input of high-potential signals to any two or three of the first input terminal, the second input terminal, and the third input terminal.

16. The adder according to claim 15, wherein the first output terminal is electrically connected to the third input terminal.

17. The adder according to claim 15, further comprising:

a first potential supply controller, wherein the carry circuit is electrically connected to the first power supply line through the first potential supply controller, and

a second potential supply controller, wherein the carry circuit is electrically connected to the second power supply line through the second potential supply controller.

18. The adder according to claim 17,

wherein the first potential supply controller comprises a third transistor,

wherein one of a source and a drain of the third transistor is electrically connected to the carry circuit and the other of the source and the drain of the third transistor is electrically connected to the first power supply line,

wherein a gate of the third transistor is configured to be supplied with a clock signal,

wherein the second potential supply controller comprises a fourth transistor,

wherein one of a source and a drain of the fourth transistor is electrically connected to the carry circuit and the other of the source and the drain of the fourth transistor is electrically connected to the second power supply line, and

wherein a gate of the fourth transistor is configured to be supplied with the clock signal.

19. The adder according to claim 17,

wherein the first potential supply controller comprises a third transistor,

wherein one of a source and a drain of the third transistor is electrically connected to the carry circuit and the other of the source and the drain of the third transistor is electrically connected to the first power supply line,

wherein a gate of the third transistor is configured to be supplied with a clock signal,

wherein the second potential supply controller comprises a fourth transistor,

wherein one of a source and a drain of the fourth transistor is electrically connected to the carry circuit and the other of the source and the drain of the fourth transistor is electrically connected to the second power supply line, and

wherein a gate of the fourth transistor is configured to be supplied with an inverted clock signal.

20. The adder according to claim 15, wherein the oxide semiconductor layer comprises indium, gallium, and zinc.