Level shifting circuitry

• US 8,638,157 B2
• Filed: 05/23/2011
• Issued: 01/28/2014
• Est. Priority Date: 05/23/2011
• Status: Active Grant

• Current Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Original Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Inventors: Duby, Jean-Claude, Rien, Mikael, Guyonnet, Damien
• Primary Examiner(s): Donovan, Lincoln
• Assistant Examiner(s): Almo, Khareem E
• Application Number:
  US13/067,305
• Publication Number:
  US 20120299631A1
• Time in Patent Office: 981 Days
• Field of Search: None
• US Class Current: 327/333
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS
• CPC Class Codes: H03K 3/356113 using additional transistors in the input circuit

Abstract

Level shifting circuitry comprises a first level shifter and a second level shifter. In response to a falling edge transition of an input signal, the first level shifter generates a primary transition of a first intermediate signal faster than the second level shifter generates a secondary transition of a second intermediate signal. In response to a rising edge of the input signal, the second level shifter generates a primary transition of the second intermediate signal faster than the first level shifter generates a secondary transition of the first intermediate signal. Output switching circuitry is provided to switch an output signal between an output high voltage level and an output low voltage level in response to the primary transition of the first intermediate signal and the primary transition of the second intermediate signal.

Claims

1. Level shifting circuitry for generating an output signal in response to an input signal, said input signal having one of an input high voltage level and an input low voltage level, said output signal having one of an output high voltage level and an output low voltage level, said level shifting circuitry comprising:

a first level shifter configured to generate a first intermediate signal having a primary transition in response to a falling edge transition of said input signal and a secondary transition in response to a rising edge transition of said input signal, said falling edge transition comprising a transition from said input high voltage level to said input low voltage level and said rising edge transition comprising a transition from said input low voltage level to said input high voltage level; and

a second level shifter configured to generate a second intermediate signal having a primary transition in response to said rising edge transition of said input signal and a secondary transition in response to said falling edge transition of said input signal;

wherein;

said first level shifter is configured to generate said primary transition of said first intermediate signal in response to said falling edge transition faster than said second level shifter generates said secondary transition of said second intermediate signal in response to said falling edge transition;

said second level shifter is configured to generate said primary transition of said second intermediate signal in response to said rising edge transition faster than said first level shifter generates said secondary transition of said first intermediate signal in response to said rising edge transition; and

said level shifting circuitry comprises output switching circuitry configured to switch said output signal between said output high voltage level and said output low voltage level in response to said primary transition of said first intermediate signal and said primary transition of said second intermediate signal, wherein said first level shifter comprises a first feedback loop configured to retain signal vales in one of a first state and a second state in dependence on said input signal, said first intermediate signal being obtained from the signal value at a first intermediate output point of said first feedback loop, and said second level shifter comprises a second feedback loop configured to retain signal values in one of said first state and said second state in dependence on said input signal, said second intermediate signal being obtained from the signal value at a second intermediate output point of said second feedback loop.

2. The level shifting circuitry according to claim 1, wherein a difference between said output high voltage level and said output low voltage level is greater than a difference between said input high voltage level and said input low voltage level.

3. The level shifting circuitry according to claim 1, wherein said first feedback loop and said second feedback loop each comprise a falling edge input point for inputting an initialising signal value in response to said falling edge transition of said input signal and a rising edge input point for inputting an initialising signal value in response to said rising edge transition of said input signal,

said first feedback loop and said second feedback loop being configured in said one of said first state and said second state in dependence on whether said initialising value is input at said falling edge input point or said rising edge input point.

4. The level shifting circuitry according to claim 3, wherein said first feedback loop and said second feedback loop each comprise a first gating device for selectively coupling said falling edge input point to a voltage supply in response to said falling edge transition of said input signal, and a second gating device for selectively coupling said rising edge input point to said voltage supply in response to said rising edge transition of said input signal.

5. The level shifting circuitry according to claim 1, wherein said output switching circuitry comprises:

a pullup transistor configured to pull said output signal to said output high voltage level in response to said primary transition of one of said first intermediate signal and said second intermediate signal; and

a pulldown transistor configured to pull said output signal to said output low voltage level in response to said primary transition of the other of said first intermediate signal and said second intermediate signal.

6. The level shifting circuitry according to claim 5, comprising an additional pullup transistor configured to selectively assist said pullup transistor in pulling said output signal to said output high voltage level;

and

an additional pulldown transistor configured to selectively assist said pulldown transistor in pulling said output signal to said output low voltage level.

7. The level shifting circuitry according to claim 6, comprising additional pullup control circuitry configured to couple a gate of said additional pullup transistor to said one of said first intermediate signal and said second intermediate signal in advance of said primary transition of said one of said first intermediate signal and said second intermediate signal, and to decouple said gate of said additional pullup transistor from said one of said first intermediate signal and said second intermediate signal in advance of said secondary transition of said one of said first intermediate signal and said second intermediate signal;

and

additional pulldown control circuitry configured to couple a gate of said additional pulldown transistor to said other of said first intermediate signal and said second intermediate signal in advance of said primary transition of said other of said first intermediate signal and said second intermediate signal, and to decouple said gate of said additional pulldown transistor from said other of said first intermediate signal and said second intermediate signal in advance of said secondary transition of said other of said first intermediate signal and said second intermediate signal.

11. The level shifting circuitry according to claim 6, wherein said additional pullup transistor has a greater drive strength than said pullup transistor and said additional pulldown transistor has a greater drive strength than said pulldown transistor.

8. Level shifting circuitry for generating an output signal in response to an input signal, said input signal having one of an input high voltage level and an input low voltage level, said output signal having one of an output high voltage level and an output low voltage level, said level shifting circuitry comprising:

a first level shifter configured to generate a first intermediate signal having a primary transition in response to a falling edge transition of said input signal and a secondary transition in response to a rising edge transition of said input signal, said falling edge transition comprising a transition from said input high voltage level to said input low voltage level and said rising edge transition comprising a transition from said input low voltage level to said input high voltage level;

a second level shifter configured to generate a second intermediate signal having a primary transition in response to said rising edge transition of said input signal and a secondary transition in response to said falling edge transition of said input signal, wherein said first level shifter is configured to generate said primary transition of said first intermediate signal in response to said falling edge transition faster than said second level shifter generates said secondary transition of said second intermediate signal in response to said falling edge transition and said second level shifter is configured to generate said primary transition of said second intermediate signal in response to said rising edge transition faster than said first level shifter generates said secondary transition of said first intermediate signal in response to said rising edge transition; and

said level shifting circuitry comprises output switching circuitry configured to switch said output signal between said output high voltage level and said output low voltage level in response to said primary transition of said first intermediate signal and said primary transition of said second intermediate signal, wherein said output switching circuitry comprises;

a pullup transistor configured to pull said output signal to said output high voltage level in response to said primary transition of one of said first intermediate signal and said second intermediate signal;

a pulldown transistor configured to pull said output signal to said output low voltage level in response to said primary transition of the other of said first intermediate signal and said second intermediate signal;

an additional pullup transistor configured to selectively assist said pullup transistor in pulling said output signal to said output high voltage level; and

an additional pulldown transistor configured to selectively assist said pulldown transistor in pulling said output signal to said output low voltage level

additional pullup control circuitry configured to couple a gate of said additional pullup transistor to said one of said first intermediate signal and said second intermediate signal in advance of said primary transition of said one of said first intermediate signal and said second intermediate signal, and to decouple said gate of said additional pullup transistor from said one of said first intermediate signal and said second intermediate signal in advance of said secondary transition of said one of said first intermediate signal and said second intermediate signal;

additional pulldown control circuitry configured to couple a gate of said additional pulldown transistor to said other of said first intermediate signal and said second intermediate signal in advance of said primary transition of said other of said first intermediate signal and said second intermediate signal, and to decouple said gate of said additional pulldown transistor from said other of said first intermediate signal and said second intermediate signal in advance of said secondary transition of said other of said first intermediate signal and said second intermediate signal; and

a delay circuit configured to delay said output signal, wherein said additional pullup control circuitry controlling whether said gate of said additional pullup transistor is coupled to said one of said first intermediate signal and said second intermediate signal in dependence on the delayed output signal, and said additional pulldown control circuitry controlling whether said gate of said additional pulldown transistor is coupled to said other of said first intermediate signal and said second intermediate signal in dependence on said delayed output signal.

9. The level shifting circuitry according to claim 8, wherein said additional pullup control circuitry comprises a first pass gate configured to selectively couple said gate of said additional pullup transistor to said one of said first intermediate signal and said second intermediate signal in response to said delayed output signal;

and

said additional pulldown control circuitry comprises a second pass gate configured to selectively couple said gate of said additional pulldown transistor to said other of said first intermediate signal and said second intermediate signal in response to said delayed output signal.

10. The level shifting circuitry according to claim 8, wherein said additional pullup control circuitry comprises a first cutoff transistor configured to switch off said additional pullup transistor in response to said delayed output signal;

and

said additional pulldown control circuitry comprises a second cutoff transistor configured to switch off said additional pulldown transistor in response to said delayed output signal.

12. Level shifting circuitry for generating an output signal in response to an input signal, said input signal having one of an input high voltage level and an input low voltage level, said output signal having one of an output high voltage level and an output low voltage level, said level shifting circuitry comprising:

first level shifting means for generating a first intermediate signal having a primary transition in response to a falling edge transition of said input signal and a secondary transition in response to a rising edge transition of said input signal, said falling edge transition comprising a transition from said input high voltage level to said input low voltage level and said rising edge transition comprising a transition from said input low voltage level to said input high voltage level; and

second level shifting means for generating a second intermediate signal having a primary transition in response to said rising edge transition of said input signal and a secondary transition in response to said falling edge transition of said input signal;

wherein;

said first level shifting means is configured to generate said primary transition of said first intermediate signal in response to said falling edge transition faster than said second level shifting means generates said secondary transition of said second intermediate signal in response to said falling edge transition;

said second level shifting means is configured to generate said primary transition of said second intermediate signal in response to said rising edge transition faster than said first level shifting means generates said secondary transition of said first intermediate signal in response to said rising edge transition; and

said level shifting circuitry comprises output switching means for switching said output signal between said output high voltage level and said output low voltage level in response to said primary transition of said first intermediate signal and said primary transition of said second intermediate signal, wherein said first level shifting means comprises a first feedback loop means for retaining signal values in one of a first state and a second state in dependence on said input signal, said first intermediate signal being obtained from the signal value at a first intermediate output point of said first feedback loop means, and said second level shifting means comprises a second feedback loop means configured to retain signal values in one of said first state and said second state in dependence on said input signal, said second intermediate signal being obtained from the signal value at a second intermediate output point of said second feedback loop means.

13. A method of generating an output signal in response to an input signal, said input signal having one of an input high voltage level and an input low voltage level, said output signal having one of an output high voltage level and an output low voltage level, said method comprising:

in response to a falling edge transition of said input signal from said input high voltage level to said input low voltage level, generating a primary transition of a first intermediate signal using a first level shifter and generating a secondary transition of a second intermediate signal using a second level shifter, said first level shifter generating said primary transition of said first intermediate signal in response to said falling edge transition faster than said second level shifter generates said secondary transition of said second intermediate signal in response to said falling edge transition;

in response to a rising edge transition of said input signal from said input low voltage level to said input high voltage level, generating a primary transition of said second intermediate signal using said second level shifter and generating a secondary transition of said first intermediate signal using said first level shifter, said second level shifter generating said primary transition of said second intermediate signal in response to said rising edge transition faster than said first level shifter generates said secondary transition of said first intermediate signal in response to said rising edge transition; and

switching said output signal between said output high voltage level and said output low voltage level in response to said primary transition of said first intermediate signal and said primary transition of said second intermediate signal, wherein said first level shifter retains signal values in a first feedback loop in one of a first state and a second state in dependence on said input signal, said first intermediate signal is obtained from the signal value at a first intermediate output point of said first feedback loop, and said second level shifter retains signal values in a second feedback loop in one of said first state and said second state in dependence on said input signal, said second intermediate signal is obtained from the signal value at a second intermediate output point of said second feedback loop.