Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals

• US 8,638,159 B2
• Filed: 06/18/2010
• Issued: 01/28/2014
• Est. Priority Date: 02/28/2008
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Ranta, Tero Tapio, Bawell, Shawn, Greene, Robert W., Brindle, Christopher N., Englekirk, Robert Mark
• Primary Examiner(s): LE, DINH THANH
• Application Number:
  US12/803,064
• Publication Number:
  US 20110043271A1
• Time in Patent Office: 1,320 Days
• Field of Search: 327355-361, 327/344, 327/362, 327/427, 327/308, 455/323, 455/326, 455/425, 455/428, 333/262
• US Class Current: 327/427
• CPC Class Codes: H01F 21/12 discontinuously variable, e.g. tapped
• CPC Class Codes: H01G 4/002 Details
• CPC Class Codes: H01G 7/00 Capacitors in which the capacitance is varied by non-mechanical means; Processes of their manufacture
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H03H 11/28 Impedance matching networks
• CPC Class Codes: H03H 7/0153 Electrical filters; Controlling thereof
• CPC Class Codes: H03H 7/38 Impedance-matching networks
• CPC Class Codes: H03J 2200/10 Tuning of a resonator by means of digitally controlled capacitor bank
• CPC Class Codes: H03J 3/20 of single resonant circuit by varying inductance only or capacitance only
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03M 1/1061 using digitally programmable trimming circuits
• CPC Class Codes: H03M 1/804 with charge redistribution

Abstract

Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.

Claims

1. A unit cell for a sub-circuit of a digitally tunable capacitor (DTC), the sub-circuit being adapted to be coupled between a first RF terminal and a second RF terminal, the unit cell comprising:

a plurality of 2N switches coupled in series with M capacitors, the switches proceeding from a first switch closest the first RF terminal and farthest from the second RF terminal to a 2N-th switch farthest from the first RF terminal and closest to the second RF terminal;

a first compensation capacitor stack, comprising (2N−

1) stacked compensation capacitors, the (2N−

1) stacked compensation capacitors being referred to as a first stacked compensation capacitor, a second stacked compensation capacitor, . . . , an i-th stacked compensation capacitor, . . . , to a (2N−

1)-th stacked compensation capacitor, proceeding in a direction from the first RF terminal to the second RF terminal,

wherein

N and M represent integers greater than or equal to one,

the M capacitors are placed between the N-th switch and the (N+1)-th switch in a manner such that a first stack of N switches from among the plurality of 2N switches is connected in series between the first RF terminal and the M capacitors, the M capacitors are connected in series between the first stack of N switches and a second stack of N switches from among the plurality of 2N switches, and the second stack of N switches is connected in series between the M capacitors and the second RF terminal,

the i-th stacked compensation capacitor is connected in parallel with the first switch and an i-th switch and all switches in between, i being 1, 2, . . . , (2N−

1), and

the first compensation capacitor stack is configured to reduce the effect of parasitic capacitances of the plurality of 2N switches on the voltage across each switch when the plurality of 2N switches is off.

2. The unit cell of claim 1, wherein the M capacitors are metal-insulator-metal (MIM) capacitors or metal-metal (MM) capacitors.

3. The unit cell of claim 1, further comprising a first set of one or more capacitors placed between the first RF terminal and the first switch and a corresponding set of one or more capacitors placed between the 2N-th switch and the second RF terminal.

4. The unit cell of claim 2, further comprising a first set of one or more capacitors placed between the first RF terminal and the first switch and a corresponding set of one or more capacitors placed between the 2N-th switch and the second RF terminal.

7. The unit cell of claim 1, wherein the second RF terminal is ground.

8. The unit cell of claim 2, wherein the second RF terminal is ground.

9. The unit cell of claim 1, wherein the sub-circuit is a significant bit sub-circuit of a digitally tunable capacitor (DTC) having multiple bits.

10. An electrical circuit comprising one or more unit cells according to claim 1.

13. The unit cell of claim 1, further comprising:

a second compensation capacitor stack, comprising (2N−

1) stacked compensation capacitors, the (2N−

1)-th stacked compensation capacitor being referred to as a first stacked compensation capacitor of the second compensation capacitor stack, a second stacked compensation capacitor of the second compensation capacitor stack, . . . , a j-th stacked compensation capacitor of the second compensation capacitor stack, . . . , to a (2N−

1)-th stacked compensation capacitor of the second compensation capacitor stack, proceeding in a direction from the first RF terminal to the second RF terminal,

wherein

the j-th stacked compensation capacitor of the second compensation capacitor stack is connected in parallel with the (2N)-th switch and the (2N−

j)-th switch and all switches in between, j being 0, 1, . . . , (2N−

2), and

the first compensation capacitor stack and the second compensation capacitor stack are configured to reduce the effect of parasitic capacitances of the switch stack on the voltage across each stacked switch when the switch stack is off.

5. A unit cell for a sub-circuit of a digitally tunable capacitor (DTC), the sub-circuit being adapted to be coupled between a first RF terminal and a second RF terminal, the unit cell comprising:

a plurality of stacked switches coupled in series with one or more capacitors, the stacked switches proceeding from a first switch closest the first RF terminal and farthest from the second RF terminal to an n-th switch farthest from the first RF terminal and closest to the second RF terminal, wherein

the one or more capacitors comprise a first set of one or more capacitors placed between the i-th and the (i+1)-th switch and a second set of one or more capacitors placed between the (n−

i)-th and the (n−

i+1)-th switch, i=1, 2, . . . , (2N−

1).

6. The unit cell of claim 5, wherein the one or more capacitors are metal-insulator-metal (MIM) capacitors or metal-metal (MM) capacitors.

14. The unit cell of claim 5, further comprising a compensation capacitor stack, comprising (n−

1) stacked compensation capacitors, the (n−

1) stacked compensation capacitors being referred to as a first stacked compensation capacitor, a second stacked compensation capacitor, . . . , a j-th stacked compensation capacitor, . . . , to a (n−

1)-th stacked compensation capacitor, proceeding in a direction from the first RF terminal to the second RF terminal,

wherein

the j-th stacked compensation capacitor is connected in parallel with the first stacked switch and the j-th stacked switch and all stacked switches in between, j being 1, 2, . . . , (n−

1), and

the compensation capacitor stack is configured to reduce the effect of parasitic capacitances of the switch stack on the voltage across each stacked switch when the switch stack is off.

11. A voltage handling method comprising:

providing a plurality of 2N stacked switches, the stacked switches proceeding from a first switch closest to a first terminal and farthest from a second terminal to a 2N-th switch farthest from the first terminal and closest to the second terminal, the first terminal being a terminal through which a voltage source is coupled to the unit cell;

providing a compensation capacitor stack comprising (2N−

1) stacked compensation capacitors, the (2N−

1) stacked compensation capacitors being referred to as a first stacked compensation capacitor, a second stacked compensation capacitor, . . . , an i-th stacked compensation capacitor, . . . , to a (2N−

1)-th stacked compensation capacitor, proceeding in a direction from the first RF terminal to the second RF terminal;

coupling the stacked switches in series with M capacitors in a manner such that the M capacitors are between the N-th switch and the (N+1)-th switch; and

configuring the compensation capacitor stack to reduce the effect of parasitic capacitances of the plurality of 2N switches on the voltage across each stacked switch when the plurality of 2N switches is off,

wherein

N and M represent integers greater than or equal to one,

a first stack of N switches from among the plurality of 2N switches is connected in series between the first RF terminal and the M capacitors, the M capacitors are connected in series between the first stack of N switches and a second stack of N switches from among the plurality of 2N switches, and the second stack of N switches is connected in series between the M capacitors and the second RF terminal, and

the i-th stacked compensation capacitor is connected in parallel with the first switch and an i-th switch and all switches in between, i being 1, 2, . . . , (2N−

1).

12. The method of claim 11, wherein the first and the second terminal are RF terminals.

15. A unit cell for a sub-circuit of a digitally tunable capacitor (DTC), the sub-circuit being adapted to be coupled between a first RF terminal and a second RF terminal, the unit cell comprising:

a plurality of 2N switches coupled in series with M capacitors, the switches proceeding from a first switch closest the first RF terminal and farthest from the second RF terminal to a 2N-th switch farthest from the first RF terminal and closest to the second RF terminal; and

a compensation capacitor stack, comprising (2N−

1) stacked compensation capacitors, the (2N−

1) stacked compensation capacitors being referred to as a first stacked compensation capacitor, a second stacked compensation capacitor, . . . , an i-th stacked compensation capacitor, . . . , to a (2N−

1)-th stacked compensation capacitor, in a direction proceeding from the first RF terminal to the second RF terminal,

wherein

N and M represent integers greater than or equal to one,

the M capacitors are placed between the N-th switch and the (N+1)-th switch in a manner such that a first stack of N switches from among the plurality of 2N switches is connected in series between the first RF terminal and the M capacitors, the M capacitors are connected in series between the first stack of N switches and a second stack of N switches from among the plurality of 2N switches, and the second stack of N switches is connected in series between the M capacitors and the second RF terminal,

the i-th stacked compensation capacitor is connected in parallel with the i-th stacked switch, i being 1, 2, . . . , (2N−

1),

the first and the (2N−

1)-th stacked compensation capacitors are equal in capacitance value and have the greatest capacitance value among stacked compensation capacitors in the compensation capacitor stack,

the j-th and the (2N−

j)-th stacked compensation capacitors are equal in capacitance values, with capacitance values decreasing as j increases, j being 2, 3, . . . N, and

capacitance values of the stacked compensation capacitors are configured to reduce the effect of parasitic capacitances of the switch stack on the voltage across each stacked switch when the plurality of 2N switches is off.