Digital power management using serial data transfer

• US 8,638,242 B2
• Filed: 10/20/2011
• Issued: 01/28/2014
• Est. Priority Date: 02/03/2006
• Status: Active Grant

• Current Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Original Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Inventors: Latham, Paul, Kenly, Stewart
• Primary Examiner(s): Mai, Lam T
• Application Number:
  US13/277,662
• Publication Number:
  US 20120039376A1
• Time in Patent Office: 831 Days
• Field of Search: 341 50- 90, 707/203, 367/14, 367/27, 367/55, 375/141, 375/145, 375/367, 375/224, 375/238, 340/690, 340/540, 340/669, 307/11, 700/22, 713/300, 713/320, 713/330, 713/340, 345/156, 345/161, 345/162
• US Class Current: 341/59
• CPC Class Codes: H03M 3/328 using dither
• CPC Class Codes: H03M 3/344 by filtering other than the noise-shaping inherent to delta-sigma modulators, e.g. anti-aliasing
• CPC Class Codes: H03M 3/506 the final digital/analogue converter being constituted by a pulse width modulator

Abstract

Methods and systems for digital control utilizing oversampling.

Claims

1. A method for collecting real-time performance data from a digital power management component, the method comprising:

providing a serial data transfer component capable of receiving/sending real-time data from/to a plurality of locations in the digital power management component;

collecting, during operation of the digital power management component, real-time data from at least one location from the plurality of locations in the digital power management component; and

providing, to a controller component, the real-time data collected from the at least one location.

2. The method of claim 1 wherein providing the real-time data comprises synchronizing the controller component to the serial data transfer component utilizing a serial data transfer component clock source as a clock reference.

3. The method of claim 1 further comprising:

providing, through the controller component, real-time data to at least one other location from the plurality of locations in the digital power management component.

4. The method of claim 3 wherein providing the real-time data comprises synchronizing the controller component to the serial data transfer component utilizing a serial data transfer component clock source as a clock reference.

5. A system for collecting real-time performance data from a digital power management component, the system comprising:

a serial data transfer component receiving/sending real-time data from/to a plurality of locations in the digital power management component; and

a controller component operatively connected to said serial data transfer component, said controller comprising;

at least one processor; and

at least one non-transitory, computer usable medium having computer readable code embodied therein, said computer readable code is configured to cause said at least one processor to;

collect, during operation of the digital power management component, real-time data from at least one location from said plurality of locations in the digital power management component.

6. The system of claim 5 wherein said computer readable code embodied on said at least one non-transitory, computer usable medium is configured to cause said at least one processor to:

provide real-time data to at least one other location from said plurality of locations in the digital power management component.

7. The system of claim 5 wherein said serial data transfer component comprises:

a shift register; and

a state sequencer capable of sequencing loading data into and out of the shift register.

8. The system of claim 7 wherein said state sequencer comprises:

a clock terminal; and

a data terminal,

wherein said state sequencer synchronizes said controller component to said serial data transfer component utilizing a serial data transfer component clock source as a clock reference.

9. The system of claim 7 wherein said state sequencer comprises:

a clock terminal; and

a data terminal,

wherein said state sequencer synchronizes said controller component to said serial data transfer component using an internal clock as a clock reference.

10. The system of claim 5 wherein said computer readable code embodied on said at least one non-transitory, computer usable medium is configured to cause said at least one processor to:

provide real-time data to at least one other location from said plurality of locations in the digital power management component.

11. The system of claim 5 wherein said serial data transfer component comprises:

a shift register; and

a state sequencer sequencing loading data into and out of the shift register.

12. The system of claim 11 wherein said state sequencer comprises:

a clock terminal; and

a data terminal,

wherein said state sequencer synchronizes said controller component to said serial data transfer component utilizing a serial data transfer component clock source as a clock reference.

13. The system of claim 11 wherein said state sequencer comprises:

a clock terminal; and

a data terminal,

wherein said state sequencer synchronizes said controller component to said serial data transfer component using an internal clock as a clock reference.