Display device

• US 8,638,322 B2
• Filed: 01/26/2011
• Issued: 01/28/2014
• Est. Priority Date: 02/05/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Umezaki, Atsushi
• Primary Examiner(s): Abdulselam, Abbas
• Assistant Examiner(s): Gonzalez, Irasema
• Application Number:
  US13/014,026
• Publication Number:
  US 20110193836A1
• Time in Patent Office: 1,098 Days
• Field of Search: 345 87-104, 345204-215, 345690-699, 377 64- 81
• US Class Current: 345/205
• CPC Class Codes: G09G 2300/0439 Pixel structures
• CPC Class Codes: G09G 2300/0814 used for selection purposes, e.g. logical AND for partial update
• CPC Class Codes: G09G 3/3611 Control of matrices with row and column drivers
• CPC Class Codes: G09G 3/3659 the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes

Abstract

A display device in which partial driving can be performed with a simplified configuration of a circuit including a wiring. One of signal processing circuits includes a first transistor that controls the potential of its respective gate signal line, and a second transistor that outputs a start signal for the subsequent stage and a reset signal for the preceding stage. A signal for controlling whether the gate signal line is in an active state (a state where a selection signal is output) or a non-active state (a state where a selection signal is not output or a non-selection signal continues to be output) is input to the first transistor. A clock signal is input to the second transistor. Thus, the number of wirings necessary for operating the device is reduced.

Claims

1. A display device comprising:

a first signal processing circuit portion having comprising a first transistor, a second transistor, a third transistor, and a first circuit portion;

a second signal processing circuit portion comprising a fourth transistor, a fifth transistor, a sixth transistor, and a second circuit portion;

a third signal processing circuit portion comprising a seventh transistor, and a third circuit portion;

a first gate signal line;

a second gate signal line; and

a first pixel comprising an eighth transistor and a first pixel electrode directly connected to a terminal of the eighth transistor;

a second pixel comprising a ninth transistor and a second pixel electrode directly connected to a terminal of the ninth transistor,

wherein the first circuit portion comprises;

a first output terminal directly connected to a gate of the first transistor and a gate of the second transistor;

a second output terminal directly connected to a gate of the third transistor; and

a first input terminal directly connected to a first terminal of the fourth transistor,

wherein the second circuit portion comprises;

a first output terminal directly connected to a gate of the fourth transistor and a gate of the fifth transistor;

a second output terminal directly connected to a gate of the sixth transistor;

a first input terminal directly connected to a first terminal of the first transistor; and

a second input terminal directly connected to a first terminal of the seventh transistor,

wherein the third circuit portion comprises;

a first output terminal directly connected to a gate of the seventh transistor; and

a first input terminal directly connected to the first terminal of the fourth transistor,

wherein a second terminal of the first transistor is directly connected to a second terminal of the seventh transistor,

wherein a first terminal of the third transistor is directly connected to a first terminal of the sixth transistor,

wherein a first terminal of the second transistor and a second terminal of the third transistor are directly connected to the first gate signal line,

wherein a first terminal of the fifth transistor and a second terminal of the sixth transistor are directly connected to the second gate signal line,

wherein a gate of the eighth transistor is directly connected to the first gate signal line;

wherein a gate of the ninth transistor is directly connected to the second gate signal line; and

wherein the first signal processing circuit portion, the second signal processing circuit portion and the third signal processing circuit portion are identical to each other,

wherein the first transistor, the fourth transistor and the seventh transistor have a same configuration in the first signal processing signal portion, the second signal processing circuit portion and the third signal processing circuit portion, respectively,

wherein the second transistor and the fifth transistor have a same configuration in the first signal processing circuit portion and the second signal processing circuit portion, respectively, and

wherein the third transistor and the sixth transistor have a same configuration in the first signal processing circuit portion and the second signal processing circuit portion, respectively.

2. The display device according to claim 1, further comprising a protection circuit, and

wherein the protection circuit is directly connected to the second gate signal line.

3. The display device according to claim 1,

wherein the second circuit portion comprises a tenth transistor, an eleventh transistor, a twelfth transistor, and an inverter circuit, and

wherein the first output terminal of the second circuit portion is directly connected to an input terminal of the inverter circuit, a first terminal of the tenth transistor, a first terminal of the eleventh transistor, and a first terminal of the twelfth transistor,

wherein the second output terminal of the second circuit portion is directly connected to an output terminal of the inverter circuit and a gate of the tenth transistor,

wherein the first input terminal of the second circuit portion is directly connected to a second terminal of the twelfth transistor and a gate of the twelfth transistor, and

wherein a second input terminal of the second circuit portion is directly connected to a gate of the eleventh transistor.

4. The display device according to claim 1,

wherein a channel width of the first transistor is smaller than a channel width of the second transistor, and

wherein a channel width of the fourth transistor is smaller than a channel width of the fifth transistor.

5. The display device according to claim 1,

wherein the first to eighth transistors have the same conductivity type.

6. The display device according to claim 1,

wherein the display device is used for an electronic device selected from a group consisting of a mobile computer, a portable image reproducing device, a goggle-type display, a portable game machine, a projector, a television set, a portable television receiver, a camera, a computer, and a mobile phone.

7. The display device according to claim 1,

wherein each of the first to eighth transistors includes an oxide semiconductor layer which functions as a channel formation layer.

8. The display device according to claim 1,

wherein the first, the second and the third circuit portions each comprise an inverter circuit,

wherein each of the inverter circuits comprises an input terminal directly connected to the first input terminal and the first output terminal of the circuit portion in which it is comprised, and

wherein each of the inverter circuits comprises an output terminal directly connected the second output terminal of the circuit portion in which it is comprised.

9. A display device comprising:

a pixel portion comprising first to k^th pixels each comprising a pixel transistor and a pixel electrode directly connected to a terminal of the pixel transistor, k being a natural number greater than 2;

first to k^th gate signal lines respectively directly connected to a gate of a respective one of the pixel transistors; and

a driver circuit comprising first to k^th identical signal processing circuit portions each comprising;

a circuit portion comprising a first input terminal, a second input terminal, a first output terminal, and a second output terminal;

a first transistor and a second transistor, each comprising a gate directly connected to the first output terminal;

a third transistor comprising a gate directly connected to the second output terminal;

wherein a terminal of the second transistor and a terminal of the third transistor of the circuit portion of the i^th identical signal processing circuit portion are directly connected to the i^th gate signal line, i being a natural number greater than 2 and less than k,

wherein the first input terminal of the circuit portion of the i^th identical signal processing circuit portion is directly connected to a terminal of the first transistor of the circuit portion of the (i−

1)^th identical signal processing circuit portion,

wherein the second input terminal of the circuit portion of the i^th identical signal processing circuit portion is directly connected to a terminal of the first transistor of the circuit portion of the (i+1)^th identical signal processing circuit portion,

wherein the terminals of the first transistors of the circuit portion of the (i−

1)^th identical signal processing circuit portion to the circuit portion of the (i+1)^th identical signal processing circuit portion are directly connected to each other.

10. The display device according to claim 9,

wherein each of the circuit portions comprises an inverter circuit.

11. The display device according to claim 9,

wherein a channel width of the first transistors is smaller than a channel width of the second transistors.

12. The display device according to claim 9,

wherein each of the first to third transistors includes an oxide semiconductor layer which functions as a channel formation layer.

13. The display device according to claim 9,

further comprising protection circuits directly connected to the gate signal lines.

14. The display device according to claim 9,

wherein the display device is used for an electronic device selected from a group consisting of a mobile computer, a portable image reproducing device, a goggle-type display, a portable game machine, a projector, a television set, a portable television receiver, a camera, a computer, and a mobile phone.

15. A display device comprising:

a pixel portion comprising first to k^th pixels each comprising a pixel transistor and a pixel electrode directly connected to a terminal of the pixel transistor, k being a natural number greater than 2;

first to k^th gate signal lines respectively directly connected to a gate of a respective one of the pixel transistors; and

a driver circuit comprising first to k^th identical signal processing circuit portions each comprising;

a circuit portion comprising a first input terminal, a second input terminal, a first output terminal, and a second output terminal;

an inverter circuit comprising an input terminal and an output terminal, the input terminal being directly connected to the first output terminal of the circuit portion;

a fourth transistor comprising a first terminal directly connected to the input terminal of the inverter circuit a second terminal directly connected to the first input terminal of the circuit portion and;

a fifth transistor comprising a terminal directly connected to the input terminal of the inverter circuit and a gate directly connected to the second input terminal of the circuit portion; and

a sixth transistor comprising a terminal directly connected to the input terminal of the inverter circuit and a gate directly connected to the output terminal of the inverter circuit and to the second output terminal of the circuit portion;

a first transistor and a second transistor, each comprising a gate directly connected to the first output terminal;

a third transistor comprising a gate directly connected to the second output terminal;

wherein a terminal of the second transistor and a terminal of the third transistor of the circuit portion of the i^th identical signal processing circuit portion are directly connected to the i^th gate signal line, i being a natural number greater than 2 and less than k,

wherein the first input terminal of the circuit portion of the i^th identical signal processing circuit portion is directly connected to a terminal of the first transistor of the circuit portion of the (i−

1)^th identical signal processing circuit portion,

wherein the second input terminal of the circuit portion of the i^th identical signal processing circuit portion is directly connected to a terminal of the first transistor of the circuit portion of the (i+1)^th identical signal processing circuit portion,

wherein the terminals of the first transistors of the circuit portion of the (i−

1)^th identical signal processing circuit portion to the circuit portion of the (i+1)^th identical signal processing circuit portion are directly connected to each other.

16. The display device according to claim 15,

wherein a channel width of the first transistors is smaller than a channel width of the second transistors.

17. The display device according to claim 15,

wherein each of the first to third transistors includes an oxide semiconductor layer which functions as a channel formation layer.

18. The display device according to claim 15,

further comprising protection circuits directly connected to the gate signal lines.

19. The display device according to claim 15,

wherein the display device is used for an electronic device selected from a group consisting of a mobile computer, a portable image reproducing device, a goggle-type display, a portable game machine, a projector, a television set, a portable television receiver, a camera, a computer, and a mobile phone.