Memory architectures and techniques to enhance throughput for cross-point arrays

• US 8,638,584 B2
• Filed: 02/02/2010
• Issued: 01/28/2014
• Est. Priority Date: 02/02/2010
• Status: Active Grant

• Current Assignee: Unity Semiconductor Corporation (Rambus Inc.)
• Original Assignee: Unity Semiconductor Corporation (Rambus Inc.)
• Inventors: Chevallier, Christophe, Namala, Sri Rama, Siau, Chang Hua, Eggleston, David
• Primary Examiner(s): Ho, Hoai V
• Application Number:
  US12/658,138
• Publication Number:
  US 20110188282A1
• Time in Patent Office: 1,456 Days
• Field of Search: 365/51, 365/148, 365/230.03, 365/230.06
• US Class Current: 365/51
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement memory architectures configured to enhance throughput for cross point arrays including memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes arrays that include memory elements being formed BEOL above a FEOL logic layer within a boundary in a plane parallel to a substrate, and array lines. Further, the integrated circuit includes array line decoders disposed in the logic layer within a region located coextensive with the boundary and between the substrate and the arrays. In some embodiments, the disposition of peripheral circuitry, such as the array line decoders, under the arrays can preserve or optimize die efficiency for throughput enhancement.

Claims

1. An integrated circuit comprising:

a front-end-of-the-line (FEOL) logic layer including active circuitry fabricated FEOL on a substrate; and

arrays of memory elements, each memory element coupled between back-end-of-the-line (BEOL) array lines that electrically couple the memory elements with the active circuitry;

wherein the memory elements are fabricated in at least one BEOL layer directly above the FEOL logic layer within a memory element region having a boundary defined by a periphery of the memory elements and positioned in a plane parallel to the substrate and the BEOL array lines;

wherein the active circuitry includes a plurality of FEOL array line decoders disposed in the FEOL logic layer within a decoder region defined by a periphery of the plurality of the FEOL array line decoders located between the substrate and the memory elements;

wherein a quantity of the plurality of FEOL array line decoders corresponds to a quantity of memory elements in the memory arrays of the memory elements configured to provide a throughput value;

wherein the memory element region and the decoder region substantially overlap; and

wherein the decoder region is less than or equal to the memory element region.

2. The integrated circuit of claim 1, wherein the throughput value is configured to vary as a function of the quantity of memory elements independent of a die size for the substrate.

3. The integrated circuit of claim 1, further comprising:

a plurality of BEOL arrays constituting an amount of memory;

wherein each BEOL array includes a size configured to provide for the throughput value.

4. The integrated circuit of claim 3, wherein the plurality of FEOL array line decoders are configured to access a subset of the plurality of BEOL arrays concurrently to communicate data at a first throughput value.

5. The integrated circuit of claim 4,

wherein the first throughput value is a function of the size of each of the plurality of BEOL arrays;

and

wherein a surface area of the substrate is independent of the size of each of the plurality of BEOL arrays.

6. The integrated circuit of claim 4,

wherein the first throughput value is greater than a second throughput value;

and

wherein the plurality of FEOL array line decoders and the memory elements provide the second throughput value;

wherein the memory elements are formed in a common BEOL plane; and

wherein the decoder region is equivalent to the memory element region.

7. The integrated circuit of claim 4,

wherein the plurality of BEOL arrays each comprise a number of memory elements configured to determine a decoder area for a corresponding FEOL array line decoder;

and

wherein an aggregate FEOL decoder area the decoder region including the decoder areas for the plurality of FEOL array line decoders is no greater than the memory element region.

8. The integrated circuit of claim 1, wherein the memory elements are positioned in at least one layer of a BEOL two-terminal cross-point memory array that is fabricated BEOL, is positioned over the FEOL logic layer, and is in contact with the substrate.

9. The integrated circuit of claim 1, further comprising:

a BEOL cross point memory array including;

X-lines;

Y-lines, of which at least one Y-line is coupled with a group of the X lines; and

a subset of the memory elements being disposed between a subset of the X-lines and a subset of the Y lines.

10. The integrated circuit of claim 9, wherein the group of the subset of the memory elements constitute a BEOL array.

11. The integrated circuit of claim 1, wherein each memory element has exactly two terminals and includes a programmable resistivity to store a state as a value of resistance.

12. The integrated circuit of claim 1, wherein the active circuitry includes a FEOL interface configured as either a DRAM interface, a NAND interface, or a NOR interface.

13. The integrated circuit of claim 1, wherein the throughput value is measured in megabytes per second or greater.

14. The integrated circuit of claim 1, wherein the substrate comprises a silicon wafer or a silicon die.

15. The integrated circuit of claim 1, wherein the substrate comprises a semiconductor substrate.

16. The integrated circuit claim 1, wherein each memory element includes a non-ohmic characteristics that exhibits a very high resistance regime for a first range of voltages and a very low resistance regime for voltages above and below the first range.

17. The integrated circuit of claim 1, wherein each memory element includes a tunnel barrier and an ion reservoir electrically in series with each other.

18. The integrated circuit of claim 17, wherein the ion reservoir includes mobile oxygen ions.

19. The integrated circuit of claim 18, wherein the tunnel barrier is permeable to the mobile oxygen ions during write operations on the memory element.

20. A device comprising:

active circuitry including multiple array line decoders fabricated front-end-of-the-line (FEOL) on a substrate; and

multiple memory arrays including memory elements, each memory element coupled between back-end-of-the-line (BEOL) array lines associated with corresponding memory arrays that electrically couple the memory elements with the array line decoders;

wherein the memory elements fabricated BEOL directly above the array line decoders within a memory region having a boundary defined by a periphery of the memory elements and positioned in a plane parallel to the substrate;

wherein the multiple array line decoders are disposed within a decoder region defined by a periphery of the plurality of the FEOL array line decoders located coextensive with the boundary;

wherein the multiple memory arrays are each addressable by different array line decoders;

wherein the memory region and the decoder region substantially overlap; and

wherein the decoder region is less than or equal to the memory element region.

21. The device of claim 20, wherein the array line decoders are configured to access a subset of the memory arrays concurrently to communicate data at a throughput value for the device.

22. The device of claim 21, wherein the throughput value for the device is based on an arrangement of the memory elements into the memory arrays.

23. The device of claim 21, wherein the throughput value for the device is based on a number of array line decoders disposed in the decoder region located coextensive with the boundary.

24. The device of claim 21, wherein the throughput value for the device is independent of a die size for the substrate.

25. The device of claim 21, wherein a surface area of the substrate is independent of a size of the memory arrays.

26. The device of claim 20, wherein at least one memory element includes a tunnel barrier and an ion reservoir electrically in series with each other.