Bit line charge accumulation sensing for resistive changing memory
First Claim
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1. A memory array comprising:
- a plurality of spin-transfer torque memory cells, each spin-transfer torque memory cells electrically between a source line and a bit line and a transistor electrically coupled to the spin-transfer torque memory cells and the bit line, the transistor having a gate electrically between a source region and a drain region and the source region being electrically between the spin-transfer torque memory cell and the gate, a word line is electrically coupled to the gate; and
a high resistance state resistive changing memory cell and a low resistance state resistive changing memory cell that provide an average voltage reference value when a read operation is applied across a selected spin-transfer torque memory cell along a same word line row connecting the transistor, the high resistance state resistive changing memory cell, and the low resistance state resistive changing memory cell.
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Abstract
A memory array includes a plurality of magneto-resistive changing memory cells. Each resistive changing memory cell is electrically between a source line and a bit line and a transistor electrically between the resistive changing memory cell and the bit line. The transistor has a gate electrically between a source region and a drain region and the source region being electrically between the r magneto-resistive changing memory cell and the gate. A word line is electrically coupled to the gate. A bit line charge accumulation sensing for magneto-resistive changing memory is also disclosed.
177 Citations
12 Claims
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1. A memory array comprising:
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a plurality of spin-transfer torque memory cells, each spin-transfer torque memory cells electrically between a source line and a bit line and a transistor electrically coupled to the spin-transfer torque memory cells and the bit line, the transistor having a gate electrically between a source region and a drain region and the source region being electrically between the spin-transfer torque memory cell and the gate, a word line is electrically coupled to the gate; and a high resistance state resistive changing memory cell and a low resistance state resistive changing memory cell that provide an average voltage reference value when a read operation is applied across a selected spin-transfer torque memory cell along a same word line row connecting the transistor, the high resistance state resistive changing memory cell, and the low resistance state resistive changing memory cell. - View Dependent Claims (2, 3, 4)
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5. A memory array comprising:
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a plurality of spin-transfer torque memory cells, each spin-transfer torque memory cell electrically between a source line and a bit line and a transistor electrically between the spin-transfer torque memory cell and the bit line; a plurality of high resistance state spin-transfer torque memory cells, each high resistance state spin-transfer torque memory cell is electrically connected to a high resistance state transistor and the high resistance state transistor is electrically coupled to a reference voltage word line; and a plurality of low resistance state spin-transfer torque memory cells, each low resistance state spin-transfer torque memory cell is electrically connected to a low resistance state transistor and the low resistance state transistor is electrically coupled to the reference voltage word line; wherein one high resistance state spin-transfer torque memory cell and one low resistance state spin-transfer torque memory cell provide an average voltage reference value when a read operation is applied across a selected spin-transfer torque memory cell along a same word line row connecting the transistor, the high resistance state transistor, and the low resistance state transistor. - View Dependent Claims (6, 7)
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8. A method of sensing a data state of resistive changing memory, comprising steps of:
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precharging a bit line to a predetermined voltage value; discharging the bit line charge through a selected spin-transfer torque memory cell and reducing the bit line precharge voltage value to a bit line voltage value;
sensing the bit line voltage value to determine a data state of the spin-transfer torque memory cell by comparing the bit line voltage value to an average reference voltage value to determine a data state of the spin-transfer torque memory cell; andprecharging a high resistance state bit line and a low resistance state bit line to a predetermined reference charge level having a reference precharge voltage value, and discharging the reference charge level through a high resistance state spin-transfer torque memory cell and a low resistance state spin-transfer torque memory cell to obtain the average reference voltage value. - View Dependent Claims (9, 10, 11, 12)
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Specification