Power management of a spare DRAM on a buffered DIMM by issuing a power on/off command to the DRAM device

• US 8,639,874 B2
• Filed: 12/22/2008
• Issued: 01/28/2014
• Est. Priority Date: 12/22/2008
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Maule, Warren Edward, Gower, Kevin C., Kim, Kyu-hyoun, VanStee, Dustin James
• Primary Examiner(s): Bradley, Matthew
• Assistant Examiner(s): Mercado, Ramon A
• Application Number:
  US12/341,515
• Publication Number:
  US 20100162020A1
• Time in Patent Office: 1,863 Days
• Field of Search: None
• US Class Current: 711/106
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels

Abstract

A computer memory, having one or more of a semiconductor memory device having an internal memory array comprising a plurality of semiconductor dynamic random access memory (DRAM) cells arranged in a matrix of rows and columns, and provided as a memory module rank of such memory devices arranged in an array on a DIMM of one or more of said semiconductor memory device on a substrate which can be coupled via a memory device data interface to a memory system as a memory subsystem, each of said memory device having a low power shut-down state that can be activated using a common memory data interface. Control of power to a DRAM issues over the data interface two commands to a DRAM power control command decode, a power-state program signal and a power-state reset signal as a power-state control commands to control the power state of said DRAM, and to activate for READ/WRITE a memory cell as a normal active or spare device.

Claims

1. A computer memory comprising:

a DIMM (Dual Inline Memory Module)

a plurality of DRAM (Dynamic Random Access Memory) chips mounted on the DIMM, the plurality of DRAM chips comprising a rank of memory including a spare DRAM in the rank of memory, each of the plurality of DRAM chips configured to be powered up or placed into a low power state via commands sent on one or more data signals (DQ signals) unique to the each of the plurality of DRAM chips comprising the rank of memory;

each of the plurality of DRAM chips mounted on the DIMM comprises a command decoder to control clocking of signals on the one or more DQ signals, and a decoder to decode the DQ signals when clocked to the decoder, a first decoder output to place the DRAM in a low power state and a second decoder output to place the DRAM in a powered up state; and

wherein the spare DRAM is placed in the low power state until a particular chip in the rank of memory fails, upon which the spare DRAM is placed in the powered up state and the particular chip in the rank of memory that failed is placed into the low power state.