System and method of using a protected non-volatile memory

• US 8,639,946 B2
• Filed: 06/24/2005
• Issued: 01/28/2014
• Est. Priority Date: 06/24/2005
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: SigmaTel Incorporated (NXP Semiconductors NV)
• Inventors: Baker, David Cureton
• Primary Examiner(s): Hirl, Joseph P.
• Assistant Examiner(s): King, John B
• Application Number:
  US11/166,872
• Publication Number:
  US 20060294397A1
• Time in Patent Office: 3,140 Days
• Field of Search: 713/186, 713/193, 713/200, 713/201
• US Class Current: 713/193
• CPC Class Codes: G06F 12/1433 for a module or a part of a module
• CPC Class Codes: G06F 2212/2022 Flash memory

Abstract

The disclosure includes a system and method of using a processor and protected memory. In a particular embodiment, the system includes a processor, a volatile memory accessible to the processor, and a first nonvolatile memory accessible to the processor. The first nonvolatile memory includes a first portion of memory that is protected and is readable when a shield bit indicates an unshielded mode of operation, but is unreadable when the shield bit indicates a shielded mode of operation and a second portion of memory that is unprotected and that is readable regardless of the value of the shield bit. The system includes a second nonvolatile memory including data to be transferred to the volatile memory.

Claims

1. A system comprising:

a processor;

a volatile memory accessible to the processor;

a first nonvolatile memory accessible to the processor, the first nonvolatile memory including;

a first portion of memory that is protected and that is accessible during power up of the system when a shield bit indicates an unshielded mode of operation, but, after the first portion of memory is accessed and before execution of program code by the processor, the first portion of memory is inaccessible when the shield bit indicates a shielded mode of operation; and

a second portion of memory that is unprotected and that is readable regardless of a value of the shield bit;

a second nonvolatile memory, the second nonvolatile memory including the program code to be transferred to the volatile memory; and

external test interface protection logic responsive to an external test clock input, wherein the shield bit is set to the shielded mode of operation after detection that a number of cycles of the external test clock input exceeds a threshold;

wherein a key set is stored within the first portion of memory, the key set comprising an authentication key to authenticate the program code and a decryption key to decrypt the program code when the program code is encrypted.

2. The system of claim 1, wherein the program code includes a plurality of authentication words.

3. The system of claim 1, wherein the threshold is less than 40 clock cycles.

4. The system of claim 3, wherein the threshold is 20 clock cycles and wherein the external test clock input is a Joint Test Action Group (JTAG) clock associated with a JTAG instruction.

5. The system of claim 1, wherein the key set is associated with a unique product manufacturer.

6. The system of claim 1, wherein the second portion of memory of the first nonvolatile memory includes audio data.

7. The system of claim 1, wherein the first nonvolatile memory is read only memory and the second nonvolatile memory is flash memory.

8. The system of claim 1, wherein the threshold is less than 20 clock cycles.

9. The system of claim 1, further comprising a write once memory device to store the shield bit.

10. A memory device comprising:

a shield bit storage;

a first memory, the first memory including;

a first portion that is protected and that is accessible based on a value of a shield bit from the shield bit storage, and

a second portion that is unprotected and that is accessible independent of the value of the shield bit; and

a second memory to store program code;

wherein the first portion of the first memory includes a key set comprising an authentication key to authenticate the program code and a decryption key to decrypt the program code when the program code is encrypted;

wherein the value of the shield bit at power up of the memory device indicates an unshielded mode of operation that allows access to the first portion of the first memory; and

wherein the value of the shield bit is changed to indicate a shielded mode of operation where the first portion of the first memory is inaccessible when a number of test cycles of an external test clock input exceeds a threshold.

11. The memory device of claim 10, further comprising a read multiplexer coupled to the first portion of the first memory, the multiplexer controlled at least in part in response to the shield bit.

12. The memory device of claim 11, wherein the multiplexer outputs a data output value from the first portion of the first memory during the unshielded mode of operation and wherein the multiplexer outputs a fixed output value indicating an error condition during the shielded mode of operation.

13. The memory device of claim 10, wherein the shield bit storage comprises a write once memory device so that the shield bit is not user modifiable after a single write operation.

14. The memory device of claim 10, wherein the value of the shield bit is changed to indicate the shielded mode of operation after the first portion of the first memory is accessed but before execution of the program code by a processor.

15. A method comprising:

powering up a processor device having access to a memory device, wherein the memory device comprises;

a shield bit storage including a shield bit;

a first memory including;

a protected portion that is accessible based on a value of the shield bit, wherein the protected portion is in an unshielded mode upon powerup of the processor device, wherein the protected portion is accessible to the processor conditioned on the protected portion being in the unshielded mode, and wherein the protected portion is inaccessible to the processor when the protected portion is in a shielded mode, and

an unprotected portion that is accessible to the processor independent of the value of the shield bit; and

a second memory configured to store program code,

wherein the protected portion includes a key set comprising;

an authentication key to authenticate the program code, and

a decryption key to decrypt the program code when the program code is encrypted; and

changing a mode from the unshielded mode to the shielded mode in response to a number of test cycles of an external clock input detected at the processor device exceeding a threshold.

16. The method of claim 15, wherein the key set is readable when the protected portion is in the unshielded mode.

17. The method of claim 15, wherein the shield bit is stored in a write once memory.

18. The method of claim 15, further comprising:

reading the key set from the protected portion when the mode is the unshielded mode; and

changing the mode from the unshielded mode to the shielded mode after transfer of data associated with the protected portion and before a processor of the processor device executes the program code.

19. The method of claim 15, wherein the threshold is less than 20 clock cycles.

20. The method of claim 18, wherein the first memory includes read only memory, and wherein the second memory includes flash memory.

21. The method of claim 15, further comprising:

receiving an attempt to access the protected portion when the protected portion is in the shielded mode; and

returning an indication of a shielded and unreadable memory condition in response to the attempt.

22. The method of claim 15, wherein the threshold is less than 40 clock cycles.