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Method and apparatus for using cache memory in a system that supports a low power state

  • US 8,640,005 B2
  • Filed: 05/21/2010
  • Issued: 01/28/2014
  • Est. Priority Date: 05/21/2010
  • Status: Active Grant
First Claim
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1. An apparatus comprising:

  • a cache memory; and

    error correction logics, responsive to a request for data from a requesting device, to receive the data stored in a cache line in the cache memory if the cache line has not been previously accessed within a current refresh time period of the cache memory, and to perform error correction for the received data, the error correction logics comprising;

    a first error correction logic to generate a syndrome to determine a count of errors in the data, and to perform error correction on the data if the count of errors is determined to be one; and

    a second error correction logic to receive the data from the first error correction logic if the count of errors is determined to be greater than one, the second error correction logic to perform multi-bit error correction for the received data;

    wherein if the cache line has been previously accessed within the current refresh time period of the cache memory, the data is free of errors and the data is to be forwarded to the requesting device without performance of the error correction by the error correction logics.

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