Method and apparatus for using cache memory in a system that supports a low power state

• US 8,640,005 B2
• Filed: 05/21/2010
• Issued: 01/28/2014
• Est. Priority Date: 05/21/2010
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Wilkerson, Christopher B., Alameldeen, Alaa R., Chishti, Zeshan A., Somasekhar, Dinesh, Wu, Wei, Lu, Shih-Lien
• Primary Examiner(s): Chung, Phung M
• Application Number:
  US12/785,182
• Publication Number:
  US 20110289380A1
• Time in Patent Office: 1,348 Days
• Field of Search: 714/763, 714/785, 714/777, 714/784, 714/746, 714/781, 714/718, 714/799, 714/769, 714/764, 714/754, 711/144
• US Class Current: 714/763
• CPC Class Codes: G06F 11/1064 in cache or content addressable memories

Abstract

A cache memory system uses multi-bit Error Correcting Code (ECC) with a low storage and complexity overhead. In an embodiment, error correction logic may include a first error correction logic to determine a number of errors in data that is stored in a cache line of a cache memory, and a second error correction logic to receive the data from the first error correction logic if the number of errors is determined to be greater than one and to perform error correction responsive to receipt of the data. The cache memory system can be operated at very low idle power, without dramatically increasing transition latency to and from an idle power state due to loss of state. Other embodiments are described and claimed.

Claims

1. An apparatus comprising:

a cache memory; and

error correction logics, responsive to a request for data from a requesting device, to receive the data stored in a cache line in the cache memory if the cache line has not been previously accessed within a current refresh time period of the cache memory, and to perform error correction for the received data, the error correction logics comprising;

a first error correction logic to generate a syndrome to determine a count of errors in the data, and to perform error correction on the data if the count of errors is determined to be one; and

a second error correction logic to receive the data from the first error correction logic if the count of errors is determined to be greater than one, the second error correction logic to perform multi-bit error correction for the received data;

wherein if the cache line has been previously accessed within the current refresh time period of the cache memory, the data is free of errors and the data is to be forwarded to the requesting device without performance of the error correction by the error correction logics.

2. The apparatus of claim 1, further comprising:

repair logic, the repair logic to fix known errors in the data prior to forwarding the data to the error correction logics.

3. The apparatus of claim 2, wherein the repair logic is to fix the known errors through use of one or more patches.

4. The apparatus of claim 1, wherein the first error correction logic includes a decoder to perform the error correction in a shorter period of time than a second period of time associated with the multi-bit error correction.

5. The apparatus of claim 1, further comprising:

a Recently Accessed Line Table (RALT) coupled to an address bus of the cache memory, the RALT to determine if the cache line has been accessed within the current refresh time period of the cache memory.

6. The apparatus of claim 1, wherein the error correction logics can detect up to six errors.

7. The apparatus of claim 1, wherein the error correction logics can correct up to five errors.

8. A method comprising:

if a cache line of a cache memory has not been previously accessed within a current refresh time period of the cache memory, performing error correction comprising;

receiving, by error correction logics, data stored in the cache line, the error correction logics comprising a first error correction logic and a second error correction logic;

generating, by the first error correction logic, a syndrome to determine a number of errors in the data;

forwarding the data, by the first error correction logic to a second error correction logic if the data has greater than one error; and

performing, by the second error correction logic, multi-bit error correction for the data responsive to receiving the data forwarded by the first error correction logic; and

responsive to a request from a requesting device, if the cache line has been previously accessed within the current refresh time period and so the data is free of errors, forwarding the data to the requesting device without performing the error correction.

9. The method of claim 8, wherein prior to receiving the data at the error correction logics, known errors in the data are repaired by repair logic using bit fix logic that employs one or more patches.

10. The method of claim 8, further comprising:

determining, by a Recently Accessed Line Table (RALT) coupled to an address bus of the cache memory, whether the cache line has been accessed within the current refresh time period of the cache memory.

11. The method of claim 8, further comprising detecting up to six errors.

12. The method of claim 8, further comprising correcting up to five errors.

13. The method of claim 8, wherein single bit error correction is performed in one cycle.

14. An article including a machine-accessible non-transitory medium having associated information, wherein the information, when accessed, results in a machine performing:

responsive to a request for data from a requesting device, if a cache line of a cache memory has not been previously accessed within a current refresh time period of the cache memory;

receiving, by error correction logics, the data stored in the

cache line, the error correction logics comprising a first error correction logic and a second error correction logic;

generating, by the first error correction logic, a syndrome to determine a number of errors in the data;

forwarding the data, by the first error correction logic to a second error correction logic if the data has greater than one error; and

performing, by the second error correction logic, multi-bit error correction for the data if the data is forwarded by the first error correction logic; and

if the cache line has been previously accessed within the current refresh time period and so the data is free of errors, forwarding the data to the requesting device without performing error correction, responsive to the request for the data.

15. The article of claim 14, wherein the information, when accessed, results in the machine further performing:

repairing, by repair logic, known errors in the data prior to the data being received by the error correction logics.

16. The article of claim 14, wherein the information, when accessed, results in determining, by a Recently Accessed Line Table (RALT) coupled to an address bus of the cache memory, whether the cache line has been accessed within the current refresh time period of the cache memory.

17. The article of claim 14, wherein the information, when accessed, results in performing, by the first error correction logic, error correction responsive to an indication of a single error in the data.

18. The article of claim 17, wherein the error is repaired in one cycle.

19. A system comprising:

an external memory; and

a processor, the processor comprising;

a cache memory to store data read from the external memory into a cache line; and

error correction logics, wherein responsive to a request for the data from a requesting device, if the cache line has not been previously accessed during a current refresh time period of the cache memory, the error correction logics are to receive the data and to perform error correction, the error correction logics comprising;

a first error correction logic to generate a syndrome to determine a number of errors in the data and to correct the data if only one error is detected in the data; and

a second error correction logic to receive the data from the first error correction logic if the number of errors in the data is determined to be greater than one, the second error correction logic to perform multi-bit error correction responsive to receipt of the data from the first error correction logic; and

wherein if the cache line has been previously accessed within the current refresh time period of the cache memory the data is free of errors, and responsive to the request the data is to be forwarded to the requesting device without performance of the error correction by the error correction logics.

20. The system of claim 19, wherein the processor further comprises repair logic to fix known errors in the data through use of one or more patches prior to forwarding the data to the error correction logics.

21. The system of claim 19, wherein if only one error is detected in the data, the first error correction logic is to, after correction of the data is complete, forward corrected data to the requesting device without being sent to the second error correction logic.

22. The system of claim 19, wherein the error correction logics can detect up to six errors.