Hardware multithreading systems and methods
First Claim
1. A multithreaded microcontroller comprising:
- a set of special-purpose multithreading registers including a set of thread state registers storing a plurality of thread states for a corresponding plurality of threads;
thread control logic connected to the set of multithreading registers, comprising;
thread state transition logic connected to the set of thread state registers and configured to control thread state transitions for the plurality of threads; and
thread instructions execution logic connected to the set of thread state registers and configured to execute a set of multithreading system call machine code instructions; and
a thread profiler which collects thread profiling data including at least one of;
a thread state transition count and a time period spent by a thread in a set of thread states.
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Abstract
According to some embodiments, a multithreaded microcontroller includes a thread control unit comprising thread control hardware (logic) configured to perform a number of multithreading system calls essentially in real time, e.g. in one or a few clock cycles. System calls can include mutex lock, wait condition, and signal instructions. The thread controller includes a number of thread state, mutex, and condition variable registers used for executing the multithreading system calls. Threads can transition between several states including free, run, ready and wait. The wait state includes interrupt, condition, mutex, I-cache, and memory substrates. A thread state transition controller controls thread states, while a thread instructions execution unit executes multithreading system calls and manages thread priorities to avoid priority inversion. A thread scheduler schedules threads according to their priorities. A hardware thread profiler including global, run and wait profiler registers is used to monitor thread performance to facilitate software development.
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Citations
20 Claims
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1. A multithreaded microcontroller comprising:
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a set of special-purpose multithreading registers including a set of thread state registers storing a plurality of thread states for a corresponding plurality of threads; thread control logic connected to the set of multithreading registers, comprising; thread state transition logic connected to the set of thread state registers and configured to control thread state transitions for the plurality of threads; and thread instructions execution logic connected to the set of thread state registers and configured to execute a set of multithreading system call machine code instructions; and a thread profiler which collects thread profiling data including at least one of;
a thread state transition count and a time period spent by a thread in a set of thread states. - View Dependent Claims (2, 3, 4)
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5. A multithreaded microcontroller comprising:
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a set of special-purpose multithreading registers including a set of thread state registers storing a plurality of thread states for a corresponding plurality of threads; thread control logic connected to the set of multithreading registers, comprising; thread state transition logic connected to the set of thread state registers and configured to control thread state transitions for the plurality of threads; and thread instructions execution logic connected to the set of thread state registers and configured to execute a set of multithreading system call machine code instructions, wherein the thread state transition logic comprises logic configured to; transition a state of a thread from a ready state to a run state when the thread is scheduled for execution; transition the state of the thread from the run state to an interrupt wait state when the thread receives an interrupt; transition the state of the thread from the run state to a condition wait state when the thread executes a wait condition instruction; transition the state of the thread from the run state to a mutex wait state when the thread executes a lock mutex instruction; transition the state of the thread from the run state to an wait instruction cache state when the thread receives an instruction cache miss signal; and transition the state of the thread from the run state to a wait memory state when the thread receives a data miss signal.
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6. A multithreaded data processing method comprising:
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storing a plurality of thread states for a corresponding plurality of threads in a set of thread state registers; controlling thread state transitions for the plurality of threads using thread state transition logic connected to the set of thread state registers; and executing a set of multithreading system call machine code instructions using thread instructions execution logic connected to the set of thread state registers; collecting thread profiling data including at least one of;
a thread state transition count and a time period spent by a thread in a set of thread states. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14, 15)
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7. A multithreaded data processing method comprising:
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storing a plurality of thread states for a corresponding plurality of threads in a set of thread state registers; controlling thread state transitions for the plurality of threads using thread state transition logic connected to the set of thread state registers; and executing a set of multithreading system call machine code instructions using thread instructions execution logic connected to the set of thread state registers, further comprising; transitioning a state of a thread from a ready state to a run state when the thread is scheduled for execution; transitioning the state of the thread from the run state to an interrupt wait state when the thread receives an interrupt; transitioning the state of the thread from the run state to a condition wait state when the thread executes a wait condition instruction; transitioning the state of the thread from the run state to a mutex wait state when the thread executes a lock mutex instruction; transitioning the state of the thread from the run state to an wait instruction cache state when the thread receives an instruction cache miss signal; and transitioning the state of the thread from the run state to a wait memory state when the thread receives a data miss signal.
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16. A multithreaded microcontroller comprising:
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an instruction fetching unit configured to receive a set of machine-code instructions for a plurality of threads, the set of instructions including a set of arithmetic and logical instructions, and a set of multithreading system call instructions; an arithmetic logic unit connected to the instruction fetching unit and configured to receive and execute the set of arithmetic and logical instructions; a hardware thread controller connected to the instruction fetching unit and the arithmetic logic unit, configured to receive and execute the set of multithreading system call instructions according to a plurality of thread states that are associated with the plurality of threads; and a thread profiler which collects thread profiling data including at least one of;
a thread state transition count and a time period spent by a thread in a set of thread states. - View Dependent Claims (17, 18, 19, 20)
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Specification