Method of forming three dimensional integrated circuit devices using layer transfer technique

• US 8,642,416 B2
• Filed: 06/28/2011
• Issued: 02/04/2014
• Est. Priority Date: 07/30/2010
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Sekar, Deepak, Cronquist, Brian, Wurman, Ze'ev
• Primary Examiner(s): Swanson, Walter H
• Application Number:
  US13/635,436
• Publication Number:
  US 20130122672A1
• Time in Patent Office: 952 Days
• Field of Search: 438/199, 438/455
• US Class Current: 438/199
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 17/06 using diode elements G11C17/14 takes precedence
• CPC Class Codes: G11C 17/14 in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
• CPC Class Codes: G11C 29/82 for EEPROMs
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/8238 Complementary field-effect transistors, e.g. CMOS
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 2223/5442 comprising non digital, non alphanumeric information, e.g. symbols
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06527 : Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06589 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/36 : Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5252 : comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 23/5286 : Arrangements of power or ground buses
• CPC Class Codes: H01L 23/535 : including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 23/544 : Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 27/0207 : Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/0694 : comprising components formed on opposite sides of a semiconductor substrate
• CPC Class Codes: H01L 27/092 : complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/105 : including field-effect components
• CPC Class Codes: H01L 27/11803 : using field effect technology
• CPC Class Codes: H01L 29/42392 : fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01066 : Dysprosium [Dy]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13062 : Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/1436 : Dynamic random-access memory [DRAM]
• CPC Class Codes: H01L 2924/1437 : Static random-access memory [SRAM]
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H03K 17/687 : the devices being field-effect transistors
• CPC Class Codes: H03K 19/0948 : using CMOS or complementary insulated gate field-effect transistors
• CPC Class Codes: H03K 19/17704 : the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/17756 : for partial configuration or partial reconfiguration
• CPC Class Codes: H03K 19/17764 : for reliability
• CPC Class Codes: H03K 19/17796 : for physical disposition of blocks
• CPC Class Codes: H10B 10/00 : Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 : comprising a MOSFET load element
• CPC Class Codes: H10B 10/125 : the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: H10B 12/05 : Making the transistor
• CPC Class Codes: H10B 12/053 : the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/50 : Peripheral circuit region structures
• CPC Class Codes: H10B 20/00 : Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/20 : Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence

Abstract

A method for formation of a semiconductor device including a first wafer including a first single crystal layer comprising first transistors and first alignment mark, the method including: implanting to form a doped layer within a second wafer; forming a second mono-crystalline layer on top of the first wafer by transferring at least a portion of the doped layer using layer transfer step, and completing the formation of second transistors on the second mono-crystalline layer including a step of forming a gate dielectric followed by second transistors gate formation step, wherein the second transistors are horizontally oriented.

Claims

1. A method for formation of a semiconductor device, the method comprising:

providing a first wafer comprising a first single crystal layer comprising first transistors and at least one first alignment mark;

implanting to form a doped layer within a second wafer;

forming a second mono-crystalline layer on top of said first wafer by transferring at least a portion of said doped layer using a layer transfer step, and

completing formation of second transistors on said second mono-crystalline layer comprising a step of forming a gate dielectric followed by a second transistors gate formation step,

wherein said second transistors are horizontally oriented.

2. The method according to claim 1, comprising providing at least one metal layer overlying said first single crystal layer, wherein said at least one metal layer comprises copper or aluminum;

and provides an interconnection for said first transistors.

3. The method according to claim 1, wherein at least one of said second transistors is a p-type transistor and at least one of said second transistors is an n-type transistor.

4. The method according to claim 1, comprising:

forming a first logic circuit comprising at least a portion of said first transistors; and

forming a second logic circuit comprising at least a portion of said second transistors, wherein said second logic circuit overlays said first logic circuit, and

performing a step of replacing;

said first logic circuit by said second logic circuit, or replacing said second logic circuit by said first logic circuit.

5. The method according to claim 1, wherein at least one of said second transistors has a double gate.

6. The method according to claim 1, wherein at least one of said second transistors is a Finfet type transistor.

7. The method according to claim 1, comprising a step of forming a thermal contact to said second mono-crystalline layer,

wherein said thermal contact is designed to conduct heat but to not conduct electricity.

8. The method according to claim 1, comprising a step of depositing at least one electrical isolation region between at least two of said second transistors, wherein said electrical isolation region is designed to conduct heat.

9. The method according to claim 1, comprising a step of depositing a heat spreader layer between said second mono-crystalline layer and said first single crystal layer.

10. The method according to claim 1, comprising a step of forming at least one thermally conductive path between a power bus and an isolation layer between two of said second transistors.

11. The method according to claim 1, comprises a memory array comprising said second transistors, wherein said memory array is a floating body DRAM array.

12. The method according to claim 1, comprising implementing a logic design on said device, wherein said step of implementing comprises a synthesis step utilizing at least two libraries, wherein one of said libraries utilized more aggressive design rules than the other.

13. The method according to claim 1, comprising designing at least one power bus based on heat removal criteria.

14. The method according to claim 1, comprising forming at least three metal layers between said first single crystal layer and said second mono-crystalline layer, wherein said at least three metal layers comprises a metal three layer overlying a metal two layer overlying a metal one layer, said metal three layer comprising a metal three pitch, said metal two layer comprising a metal two pitch, said metal one layer comprising a metal one pitch, and wherein said metal two pitch is smaller than said first metal pitch and said third metal pitch.

15. A method for formation of a semiconductor device, the method comprising:

a first wafer comprising a first mono-crystalline layer comprising first transistors, and

comprising a step of implant to form second transistors within a second mono-crystalline layer, and

transferring the second mono-crystalline layer on top of said first mono-crystalline layer,

wherein said method comprises using at least ten masks, each with its own unique patterns, and

wherein said method is used for formation of at least two devices which each have a substantially different amount of logic, memory or Input-Output cells, and

wherein each of said two devices has been formed using said at least ten masks, and

wherein said two devices have the same number of mono-crystalline layers.

16. The method according to claim 15, comprising the step of formation of dice lines by etching pre-patterned layers.

17. The method according to claim 15, wherein at least one of said two devices comprises unused potential dice lines.

18. The method according to claim 15, wherein the formation of at least one of said two devices comprises the step of using a custom mask to form at least one connection over unused potential dice lines, and wherein the formation of the other of said two devices does not use said custom mask.

19. The method according to claim 15, wherein at least one of said two devices comprises at least two micro-control-units (MCUs), and wherein said two micro-control-units comprise a fixed interconnection between them.

20. The method according to claim 15, further comprising the step of forming a Through Silicon Via (TSV) to form a connection between said second transistors and said first transistors.