Method of manufacturing an integrated circuit device

• US 8,642,438 B2
• Filed: 12/13/2011
• Issued: 02/04/2014
• Est. Priority Date: 01/11/2011
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: Lee, Young-Ho, Kim, Keon-Soo, Cho, Seong-Soon, Shin, Jin-Hyun
• Primary Examiner(s): Geyer, Scott B
• Assistant Examiner(s): Seven, Evren
• Application Number:
  US13/324,035
• Publication Number:
  US 20120178234A1
• Time in Patent Office: 784 Days
• Field of Search: 438381-399
• US Class Current: 438/382
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H10B 41/42 Simultaneous manufacture of periphery and memory cells

Abstract

In an integrated circuit device and method of manufacturing the same, a resistor pattern is positioned on a device isolation layer of a substrate. The resistor pattern includes a resistor body positioned in a recess portion of the device isolation layer and a connector making contact with the resistor body and positioned on the device isolation layer around the recess portion. The connector has a metal silicide pattern having electric resistance lower than that of the resistor body at an upper portion. A gate pattern is positioned on the active region of the substrate and includes the metal silicide pattern at an upper portion. A resistor interconnection is provided to make contact with the connector of the resistor pattern. A contact resistance between the connector and the resistor interconnection is reduced.

Claims

1. A method of manufacturing an integrated circuit device, comprising:

preparing a substrate having an active region defined by a device isolation layer;

forming a resistor pattern on the device isolation layer, the resistor pattern including a resistor body positioned in a recess portion of the device isolation layer and at least a connector making contact with the resistor body and positioned on the device isolation layer around the recess portion, the connector having a metal silicide pattern having electric resistance lower than that of the resistor body at an upper portion thereof;

forming a gate pattern on the active region of the substrate, the gate pattern including the metal silicide pattern at an upper portion thereof; and

forming a resistor interconnection making contact with the connector of the resistor pattern,

wherein the connector and the resistor interconnection are made of a same metal so as to reduce contact resistance therebetween.

2. The method of claim 1, wherein a plurality of the gate patterns is formed on a cell area of the substrate in which a plurality of cell transistors is formed and on a peripheral circuit portion of a peripheral area of the substrate in which a plurality of peripheral transistors electrically connected to the cell transistor is formed, and the resistor pattern is formed on a resistor portion of the peripheral area of the substrate simultaneously with the gate pattern.

3. The method of claim 2, wherein forming the resistor pattern includes:

forming the device isolation layer on a field region of the substrate and a tunnel insulation pattern and a floating gate pattern on the active region of the substrate in such a manner that the device isolation layer and the tunnel insulation pattern and a floating gate pattern are shaped into a line and a sidewall of the floating gate pattern is exposed over the device isolation layer in the cell area and the device isolation layer is formed into a bulk shape in the resistor portion of the peripheral area of the substrate;

sequentially forming a dielectric layer and a first conductive layer on the floating gate pattern and the device isolation layer;

partially removing the bulk-shaped device isolation layer at the resistor portion of the peripheral area of the substrate while partially exposing the floating gate pattern on the active region of the substrate, thereby forming the recess portion on the bulk-shaped device isolation layer;

forming a second conductive layer on the cell area and the peripheral area of the substrate along a surface profile thereof;

patterning the second conductive layer, the first conductive layer and the dielectric layer, thereby forming a preliminary gate pattern on the active region of the substrate and forming a preliminary resistor pattern on the bulk-shaped device isolation layer, the preliminary resistor pattern including a preliminary resistor body at a bottom of the recess portion and a preliminary connector on the bulk-shaped device isolation pattern around the recess portion thereof; and

forming a metal silicide pattern on the preliminary gate pattern and the preliminary resistor pattern, so that the resistor pattern on the resistor portion of the peripheral area of the substrate is formed simultaneously with the gate pattern on the active region of the substrate.

4. The method of claim 3, wherein forming the device isolation layer includes:

etching the substrate on which the tunnel insulation layer and the floating gate layer are stacked by a self-aligned process, thereby forming a trench in the field region of the substrate simultaneously with the tunnel insulation pattern and the floating gate pattern defined by the trench;

filling up the trench with insulation materials, thereby forming the device isolation layer in the trench; and

partially removing an upper portion of the device isolation layer in the cell area of the substrate, thereby exposing the sidewall of the floating gate pattern over the device isolation layer in the cell area of the substrate.

5. The method of claim 3, wherein partially removing the bulk-shaped device isolation layer includes:

forming a first mask pattern on the first conducive layer, the first mask pattern including a plurality of openings through which the first conductive layer is partially exposed on the active region and the resistor portion of the peripheral area of the substrate, respectively; and

sequentially removing the first conductive layer, the dielectric layer and the bulk-shaped device isolation layer by a first etching process using the first mask pattern as an etching mask at the resistor portion of the peripheral area while simultaneously removing the first conductive layer and the dielectric layer at the active region of the substrate by the first etching process, so that the recess portion is formed on the bulk-shaped device isolation layer at the resistor portion of the peripheral area and the floating gate pattern is partially exposed at the active region of the substrate.

6. The method of claim 5, wherein the first mask pattern includes a first opening through which the floating gate pattern corresponding to a string selection transistor is exposed in the cell area, a second opening through which the floating gate pattern corresponding to the peripheral transistor is exposed in the peripheral circuit portion of the peripheral area and a third opening through which a central portion of the bulk-shaped device isolation layer is exposed.

7. The method of claim 6, wherein the second conductive layer is formed into a control gate of a stack gate pattern together with the first conducive layer in the cell area while the second conductive layer making contact with the floating gate pattern through the first opening is formed into the string selection transistor and the second conductive layer making contact with the floating gate pattern through the second opening is formed into the peripheral transistor.

8. The method of claim 3, wherein patterning the second conductive layer, the first conductive layer and the dielectric layer includes:

forming a second mask pattern on the second conductive layer; and

sequentially performing a dry etching process against the second conductive layer, the first conductive layer and the dielectric layer using the second mask pattern as an etching mask, thereby forming the preliminary gate pattern and the preliminary resistor pattern.

9. The method of claim 8, wherein forming the metal silicide pattern includes:

forming a protection layer to cover the preliminary gate pattern and the preliminary resistor pattern;

planarizing the protection layer until the preliminary gate pattern and the preliminary resistor pattern are exposed, thereby forming a protection pattern from which a second conductive pattern is protruded;

forming a metal layer on the protection pattern such that the second conductive pattern is covered with the metal layer; and

performing a heat treatment to the metal layer, thereby forming the metal silicide layer on the second conductive pattern.

10. The method of claim 9, before forming the protection layer, further comprising:

forming spacers on sidewalls of the preliminary gate pattern and the preliminary resistor pattern; and

forming an etch stop layer on the preliminary gate pattern, the preliminary resistor pattern, the tunnel insulation layer and the etch stop layer.

11. The method of claim 9, wherein the protection layer comprises tetra ethyl ortho silicate deposited by plasma enhanced chemical vapor deposition process (PETEOS).

12. The method of claim 9, wherein planarizing the protection layer is performed by one of a chemical mechanical polishing (CMP) process, a chemically enhanced polishing (CEP) process and an etch-back process.

13. The method of claim 9, wherein the metal layer includes at least a material selected from the group consisting of tungsten (W), nickel (Ni), cobalt (Co), titanium (Ti), tantalum (Ta) and combinations thereof.

14. The method of claim 9, wherein forming the resistor interconnection includes:

forming an insulation interlayer on the protection pattern and the metal silicide pattern;

patterning the insulation interlayer, thereby forming an opening through which the metal silicide pattern on the connector is exposed; and

forming a first conductive pattern in the opening, the first conductive pattern making contact with the metal silicide pattern of the connector.

15. The method of claim 14, further comprising forming a second conductive pattern making contact with the active region of the substrate through the insulation interlayer, wherein the second conductive pattern is formed simultaneously with the first conductive pattern.

16. A method of manufacturing an integrated circuit device, comprising:

forming one or more device isolation layers on a cell area and a peripheral area of a substrate;

forming a resistor pattern having a resistor body having a first electric resistance and a connector having a second electric resistance lower than the first electric resistance, on the device isolation layers of a resistor portion of the peripheral area of the substrate; and

forming a resistor interconnection to contact the connector of the resistor pattern to reduce a contact resistance therebetween,

wherein the forming of the one or more device isolation layers on the peripheral layer of the substrate comprises;

forming a recess portion and a protrusion portion in the respective device isolation layers;

forming the resistor body on the recess portion and the protrusion portion; and

forming the connector on the protrusion portion to have a depth of recess with the resistor body in the recess portion,

wherein the connector and the resistor interconnection are made of a same metal so as to reduce contact resistance therebetween.

17. The method of claim 16, further comprising:

forming one or more gate patterns on active regions of the cell area of the substrate,

wherein the forming of the device isolation layers in the cell area comprises forming the device isolation layers in field regions of the cell area between the adjacent active regions.

18. The method of claim 17, wherein the forming of the gate patterns comprises forming a floating gate pattern of the gate pattern to be disposed between the device isolation layers such that an upper portion of the floating gate pattern of the gate pattern is exposed from an upper portion of one or more the device isolation layers.