Self-aligned STI with single poly for manufacturing a flash memory device

• US 8,642,441 B1
• Filed: 12/15/2006
• Issued: 02/04/2014
• Est. Priority Date: 12/15/2006
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.), Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Spansion LLC (Infineon Technologies AG)
• Inventors: Thurgate, Tim, Fang, Shenqing, Chang, Kuo-Tung, Suh, YouSeok, Ding, Meng, Shiraiwa, Hidehiko, Joshi, Amol, Sachar, Harpreet, Matsumoto, David, Singh, Lovejeet, Yang, Chih-Yuh
• Primary Examiner(s): Richards, N Drew
• Assistant Examiner(s): SINGAL, ANKUSH K
• Application Number:
  US11/639,667
• Time in Patent Office: 2,608 Days
• Field of Search: 438/270, 438/435
• US Class Current: 438/400
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H10B 43/00 EEPROM devices comprising charge-trapping gate insulators
• CPC Class Codes: H10B 43/30 characterised by the memory core region

Abstract

A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, the charge-trapping structure and other layers can be formed by a self-aligned process.

Claims

1. A memory device, comprising:

a semiconductor substrate;

a plurality of active regions disposed over the semiconductor substrate, each active region of the plurality of active regions having a plurality of sharp corners;

a plurality of trenches separating the plurality of active regions and filled with an insulator material, the plurality of sharp corners of the plurality of active regions being exposed by a formation of the plurality of trenches; and

a plurality of self-aligned charge trapping structures disposed over the plurality of active regions, the plurality of self-aligned charge trapping structures being separated from each other, each self-aligned charge trapping structure corresponding specifically to a different active region of the plurality of active regions,

wherein the-plurality of sharp corners of the plurality of active regions are rounded by the rounding process before the plurality of trenches are filled with the insulator material and the plurality of self-aligned charge trapping structures are formed.

2. The memory device of claim 1, wherein the plurality of self-aligned charge trapping structures is aligned through a sacrificial top oxide, polish, recess, nitride etch, sacrificial top oxide etch, and top oxide process.

3. The memory device of claim 1, wherein the plurality of corners is rounded through a liner oxide process.

4. The memory device of claim 1, wherein the plurality of charge trapping structures comprises an oxide-nitride-oxide structure.

5. The device of claim 1, further comprising a tunnel oxide formed between the semiconductor substrate and a self-aligned charge trapping structure of the plurality of self-aligned charge trapping structures.

6. The memory device of claim 2, wherein the sacrificial top oxide etch comprises polishing the sacrificial top oxide by performing a chemical mechanical planarization (CMP) technique.

7. The memory device of claim 2, wherein the sacrificial top oxide etch comprises polishing the sacrificial top oxide by performing a plasma dry etch.

8. The memory device of claim 2, wherein the sacrificial top oxide etch comprises partially removing the SiRN layer.

9. The memory device of claim 4, wherein the nitride of the oxide-nitride-oxide structure is comprised of a silicon rich nitride (SiRN) layer.

10. The memory device of claim 4, wherein the nitride of the oxide-nitride-oxide structure is comprised of nitride on top of silicon rich nitride.

11. The memory device of claim 4, wherein the nitride of the oxide-nitride-oxide structure is comprised of a plurality of nitride layers having different amounts of silicon.

12. The memory device of claim 4, wherein each active region of the plurality of active regions has a corresponding SiRN layer.