Method for forming a semiconductor device with an isolation region on a gate electrode
First Claim
1. A method for manufacturing a semiconductor device, comprising:
- providing a semiconductor substrate having a trench with a sidewall isolation, the trench having an upper portion and a lower portion, wherein a field electrode is arranged in the lower portion of the trench;
removing the sidewall isolation in the upper portion of the trench above the field electrode;
forming a gate dielectric on the laid open sidewall in the upper portion of the trench above the field electrode and the sidewall isolation;
forming a gate electrode adjacent to the gate dielectric in the upper portion of the trench above the field electrode and the sidewall isolation, an upper surface of the gate electrode being located at a depth d1 below the surface of the semiconductor substrate such that the gate dielectric is exposed in the upper portion of the trench, wherein the gate electrode comprises doped polysilicon;
performing an implantation after the formation of the gate electrode to provide the upper surface of the gate electrode with a higher doping concentration;
removing, subsequent to forming the gate electrode and subsequent to performing the implantation, the gate dielectric above the gate electrode including the exposed portion of the gate dielectric in the upper portion of the trench; and
forming, subsequent to removing the gate dielectric, an isolation simultaneously on the gate electrode and the semiconductor substrate such that an absolute value of height difference d2 between the isolation over the gate electrode and the isolation over the semiconductor substrate is smaller than the depth d1.
1 Assignment
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Accused Products
Abstract
A method for forming a semiconductor device. One embodiment provides a semiconductor substrate having a trench with a sidewall isolation. The sidewall isolation is removed in a portion of the trench. A gate dielectric is formed on the laid open sidewall. A gate electrode is formed adjacent to the date dielectric. The upper surface of the gate electrode is located at a depth d1 below the surface of the semiconductor substrate. The gate oxide is removed above the gate electrode. An isolation is formed simultaneously on the gate electrode and the semiconductor substrate such that the absolute value of height difference d2 between the isolation over the gate electrode and the isolation over the semiconductor substrate is smaller than the depth d1.
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Citations
23 Claims
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1. A method for manufacturing a semiconductor device, comprising:
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providing a semiconductor substrate having a trench with a sidewall isolation, the trench having an upper portion and a lower portion, wherein a field electrode is arranged in the lower portion of the trench; removing the sidewall isolation in the upper portion of the trench above the field electrode; forming a gate dielectric on the laid open sidewall in the upper portion of the trench above the field electrode and the sidewall isolation; forming a gate electrode adjacent to the gate dielectric in the upper portion of the trench above the field electrode and the sidewall isolation, an upper surface of the gate electrode being located at a depth d1 below the surface of the semiconductor substrate such that the gate dielectric is exposed in the upper portion of the trench, wherein the gate electrode comprises doped polysilicon; performing an implantation after the formation of the gate electrode to provide the upper surface of the gate electrode with a higher doping concentration; removing, subsequent to forming the gate electrode and subsequent to performing the implantation, the gate dielectric above the gate electrode including the exposed portion of the gate dielectric in the upper portion of the trench; and forming, subsequent to removing the gate dielectric, an isolation simultaneously on the gate electrode and the semiconductor substrate such that an absolute value of height difference d2 between the isolation over the gate electrode and the isolation over the semiconductor substrate is smaller than the depth d1. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A method for manufacturing a semiconductor device, comprising:
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providing a semiconductor substrate having a trench with a sidewall isolation, the trench having an upper portion and a lower portion, wherein a field electrode is arranged in the lower portion of the trench; removing the sidewall isolation in the upper portion of the trench above the field electrode; forming a gate dielectric on the laid open sidewall in the upper portion of the trench above the field electrode and the sidewall isolation; forming a gate electrode adjacent to the gate dielectric in the upper portion of the trench above the field electrode and the sidewall isolation, an upper surface of the gate electrode being located at a depth d1 below the surface of the semiconductor substrate such that the gate dielectric is exposed in the upper portion of the trench, wherein the gate electrode comprises doped polysilicon; performing an implantation after the formation of the gate electrode to provide the upper surface of the gate electrode with a higher doping concentration; removing, subsequent to forming the gate electrode and subsequent to performing the implantation, the gate dielectric above the gate electrode including the exposed portion of the gate dielectric in the upper portion of the trench; and forming, subsequent to removing the gate dielectric, an isolation by thermal oxidation, simultaneously on the gate electrode and the semiconductor substrate such that an absolute value of height difference d2 between the isolation over the gate electrode and the isolation over the semiconductor substrate is smaller than the depth d1. - View Dependent Claims (16, 17, 18)
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19. A method for manufacturing a semiconductor device, comprising:
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providing a semiconductor substrate having a trench with a sidewall isolation, the trench having an upper portion and a lower portion, wherein a field electrode is arranged in the lower portion of the trench; removing the sidewall isolation in the upper portion of the trench above the field electrode; forming a gate dielectric on the laid open sidewall in the upper portion of the trench above the field electrode and the sidewall isolation; forming a gate electrode adjacent to the gate dielectric in the upper portion of the trench above the field electrode and the sidewall isolation, an upper surface of the gate electrode being located at a depth d1 below the surface of the semiconductor substrate such that the gate dielectric is exposed in the upper portion of the trench, wherein the gate electrode comprises doped polysilicon; performing an implantation after the formation of the gate electrode to provide the upper surface of the gate electrode with a higher doping concentration; removing, subsequent to forming the gate electrode and subsequent to performing the implantation, the gate dielectric above the gate electrode including the exposed portion of the gate dielectric in the upper portion of the trench; forming, subsequent to removing the gate dielectric, a first isolation simultaneously on the gate electrode and the semiconductor substrate such that an absolute value of height difference d2 between the first isolation over the gate electrode and the first isolation over the semiconductor substrate is smaller than the depth d1; and forming a second isolation on the first isolation. - View Dependent Claims (20, 21)
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22. A method for manufacturing a semiconductor device, comprising:
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providing a semiconductor substrate; removing a sidewall isolation in an upper portion of a trench in the semiconductor substrate; forming a gate dielectric on the sidewall in the upper portion of the trench above the sidewall isolation; forming a gate electrode adjacent to the gate dielectric in the upper portion of the trench above the sidewall isolation, and performing subsequently a shallow recess process such that an upper surface of the gate electrode is located at a depth d1 below the surface of the semiconductor substrate, wherein the gate electrode comprises doped polysilicon; performing an implantation after the formation of the gate electrode to provide the upper surface of the gate electrode with a higher doping concentration; removing, subsequent to forming the gate electrode and subsequent to performing the implantation, the gate dielectric above the gate electrode including an exposed portion of the gate dielectric in the upper portion of the trench; and forming, subsequent to removing the gate dielectric, an isolation on the gate electrode and the semiconductor substrate such that an absolute value of height difference d2 between the isolation over the gate electrode and the isolation over the semiconductor substrate is smaller than the depth d1. - View Dependent Claims (23)
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Specification