Method for forming a semiconductor device with an isolation region on a gate electrode

• US 8,642,459 B2
• Filed: 08/28/2008
• Issued: 02/04/2014
• Est. Priority Date: 08/28/2008
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Poelzl, Martin
• Primary Examiner(s): Rizkallah, Kimberly
• Assistant Examiner(s): NGUYEN, DUY T V
• Application Number:
  US12/200,509
• Publication Number:
  US 20100055892A1
• Time in Patent Office: 1,986 Days
• Field of Search: 438/258, 438/595, 257/E21.294
• US Class Current: 438/595
• CPC Class Codes: H01L 21/28035 the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities H01L21/28105 takes precedence
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method for forming a semiconductor device. One embodiment provides a semiconductor substrate having a trench with a sidewall isolation. The sidewall isolation is removed in a portion of the trench. A gate dielectric is formed on the laid open sidewall. A gate electrode is formed adjacent to the date dielectric. The upper surface of the gate electrode is located at a depth d1 below the surface of the semiconductor substrate. The gate oxide is removed above the gate electrode. An isolation is formed simultaneously on the gate electrode and the semiconductor substrate such that the absolute value of height difference d2 between the isolation over the gate electrode and the isolation over the semiconductor substrate is smaller than the depth d1.

Claims

1. A method for manufacturing a semiconductor device, comprising:

providing a semiconductor substrate having a trench with a sidewall isolation, the trench having an upper portion and a lower portion, wherein a field electrode is arranged in the lower portion of the trench;

removing the sidewall isolation in the upper portion of the trench above the field electrode;

forming a gate dielectric on the laid open sidewall in the upper portion of the trench above the field electrode and the sidewall isolation;

forming a gate electrode adjacent to the gate dielectric in the upper portion of the trench above the field electrode and the sidewall isolation, an upper surface of the gate electrode being located at a depth d1 below the surface of the semiconductor substrate such that the gate dielectric is exposed in the upper portion of the trench, wherein the gate electrode comprises doped polysilicon;

performing an implantation after the formation of the gate electrode to provide the upper surface of the gate electrode with a higher doping concentration;

removing, subsequent to forming the gate electrode and subsequent to performing the implantation, the gate dielectric above the gate electrode including the exposed portion of the gate dielectric in the upper portion of the trench; and

forming, subsequent to removing the gate dielectric, an isolation simultaneously on the gate electrode and the semiconductor substrate such that an absolute value of height difference d2 between the isolation over the gate electrode and the isolation over the semiconductor substrate is smaller than the depth d1.

2. The method of claim 1, wherein the energy of the dopand atoms lies in the range between 20 and 60 keV.

3. The method of claim 1, wherein the dose of the implantation lies in the range between 5*10¹⁴ and 5*10¹⁶ cm⁻

2.

4. The method of claim 3, wherein the dose of the implantation lies in the range between 5*10¹⁵ and 1*10₁₆ cm⁻

2.

5. The method of claim 1, wherein the semiconductor substrate comprises silicon.

6. The method of claim 1, wherein the sidewall isolation comprises silicon oxide.

7. The method of claim 1, wherein the isolation comprises silicon oxide.

8. The method of claim 1, comprising forming the isolation in a single step.

9. The method of claim 1, comprising forming the gate electrode by deposition followed by chemical mechanical polishing.

10. The method of claim 1, comprising removing a portion of the isolation and thereafter performing implantation defining the conduction type of the semiconductor region adjacent to the gate dielectric.

11. The method of claim 1, wherein the thickness of the isolation over the gate electrode is larger than the sum of the thickness of the isolation over the semiconductor substrate and d1.

12. The method of claim 1, comprising uncovering at least a portion of surface of the semiconductor substrate from the isolation and forming at least one contact hole in the uncovered portion of semiconductor substrate.

13. The method of claim 12, comprising using the isolation over the gate electrode as a mask for the formation of the contact hole.

14. The method of claim 1, wherein forming the gate electrode comprises performing a shallow recess process such that the gate dielectric is exposed in the upper portion of the trench.

15. A method for manufacturing a semiconductor device, comprising:

providing a semiconductor substrate having a trench with a sidewall isolation, the trench having an upper portion and a lower portion, wherein a field electrode is arranged in the lower portion of the trench;

removing the sidewall isolation in the upper portion of the trench above the field electrode;

forming a gate dielectric on the laid open sidewall in the upper portion of the trench above the field electrode and the sidewall isolation;

forming a gate electrode adjacent to the gate dielectric in the upper portion of the trench above the field electrode and the sidewall isolation, an upper surface of the gate electrode being located at a depth d1 below the surface of the semiconductor substrate such that the gate dielectric is exposed in the upper portion of the trench, wherein the gate electrode comprises doped polysilicon;

performing an implantation after the formation of the gate electrode to provide the upper surface of the gate electrode with a higher doping concentration;

removing, subsequent to forming the gate electrode and subsequent to performing the implantation, the gate dielectric above the gate electrode including the exposed portion of the gate dielectric in the upper portion of the trench; and

forming, subsequent to removing the gate dielectric, an isolation by thermal oxidation, simultaneously on the gate electrode and the semiconductor substrate such that an absolute value of height difference d2 between the isolation over the gate electrode and the isolation over the semiconductor substrate is smaller than the depth d1.

16. The method of claim 15, wherein the temperature of the thermal oxidation process is higher than 900°

C.

17. The method of claim 15, wherein the temperature of the thermal oxidation process is lower than 1100°

C.

18. The method of claim 15, comprising performing the thermal oxidation process over period of 200 min to 280 min.

19. A method for manufacturing a semiconductor device, comprising:

providing a semiconductor substrate having a trench with a sidewall isolation, the trench having an upper portion and a lower portion, wherein a field electrode is arranged in the lower portion of the trench;

removing the sidewall isolation in the upper portion of the trench above the field electrode;

forming a gate dielectric on the laid open sidewall in the upper portion of the trench above the field electrode and the sidewall isolation;

forming a gate electrode adjacent to the gate dielectric in the upper portion of the trench above the field electrode and the sidewall isolation, an upper surface of the gate electrode being located at a depth d1 below the surface of the semiconductor substrate such that the gate dielectric is exposed in the upper portion of the trench, wherein the gate electrode comprises doped polysilicon;

performing an implantation after the formation of the gate electrode to provide the upper surface of the gate electrode with a higher doping concentration;

removing, subsequent to forming the gate electrode and subsequent to performing the implantation, the gate dielectric above the gate electrode including the exposed portion of the gate dielectric in the upper portion of the trench;

forming, subsequent to removing the gate dielectric, a first isolation simultaneously on the gate electrode and the semiconductor substrate such that an absolute value of height difference d2 between the first isolation over the gate electrode and the first isolation over the semiconductor substrate is smaller than the depth d1; and

forming a second isolation on the first isolation.

20. The method of claim 19, comprising forming the second isolation as a silicate glass layer.

21. The method of claim 19, comprising forming the second isolation as an undoped silicate glass layer.

22. A method for manufacturing a semiconductor device, comprising:

providing a semiconductor substrate;

removing a sidewall isolation in an upper portion of a trench in the semiconductor substrate;

forming a gate dielectric on the sidewall in the upper portion of the trench above the sidewall isolation;

forming a gate electrode adjacent to the gate dielectric in the upper portion of the trench above the sidewall isolation, and performing subsequently a shallow recess process such that an upper surface of the gate electrode is located at a depth d1 below the surface of the semiconductor substrate, wherein the gate electrode comprises doped polysilicon;

performing an implantation after the formation of the gate electrode to provide the upper surface of the gate electrode with a higher doping concentration;

removing, subsequent to forming the gate electrode and subsequent to performing the implantation, the gate dielectric above the gate electrode including an exposed portion of the gate dielectric in the upper portion of the trench; and

forming, subsequent to removing the gate dielectric, an isolation on the gate electrode and the semiconductor substrate such that an absolute value of height difference d2 between the isolation over the gate electrode and the isolation over the semiconductor substrate is smaller than the depth d1.

23. The method of claim 22, comprising:

uncovering at least a portion of surface of the semiconductor substrate and forming at least one contact hole in the uncovered portion of semiconductor substrate; and

using the isolation over the gate electrode as a mask for the formation of the contact hole.