Thin film transistor having a patterned passivation layer

• US 8,643,006 B2
• Filed: 06/20/2011
• Issued: 02/04/2014
• Est. Priority Date: 04/22/2011
• Status: Active Grant

• Current Assignee: AU Optronics Corporation
• Original Assignee: AU Optronics Corporation
• Inventors: Chen, Chia-Hsiang, Hung, Ming-Chin, Tu, Chun-Hao, Lin, Wei-Ting, Chang, Jiun-Jye
• Primary Examiner(s): HA, NATHAN W
• Application Number:
  US13/163,727
• Publication Number:
  US 20120267621A1
• Time in Patent Office: 960 Days
• Field of Search: 257/59, 257/43, 257/72
• US Class Current: 257/43
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A thin film transistor is provided. The thin film transistor includes a substrate, a gate, a gate insulating layer, a source and a drain, a channel layer, and first and second patterned passivation layers. The gate is disposed on the substrate. The gate insulating layer is disposed on the gate. The source and the drain are disposed on the gate insulating layer. The channel layer is disposed above or under the source and the drain, wherein a portion of the channel layer is exposed between the source and the drain. The first patterned passivation layer is disposed on the portion of the channel layer, wherein the first patterned passivation layer includes metal oxide, and the first patterned passivation layer has a thickness ranging from 50 angstroms to 300 angstroms. The second patterned passivation layer covers the first patterned passivation layer, the gate insulating layer, and the source and the drain.

Claims

1. A thin film transistor, comprising:

a substrate;

a gate, disposed on the substrate;

a gate insulating layer, disposed on the gate;

a source and a drain, disposed on the gate insulating layer, wherein the source, the drain and the gate insulating layer together form a hollow;

a channel layer, disposed under the source and the drain, wherein a portion of the channel layer is exposed by the hollow between the source and the drain;

a first patterned passivation layer, disposed completely within the hollow and contacting the portion of the channel layer, wherein the first patterned passivation layer includes a metal oxide, the first patterned passivation layer has a thickness ranging from 50 angstroms to 300 angstroms; and

a second patterned passivation layer, covering the first patterned passivation layer and disposed within the hollow.

2. The thin film transistor as claimed in claim 1, wherein the metal oxide comprises Al2O3, TiOx, HfOx, or TaOx.

3. The thin film transistor as claimed in claim 1, wherein the second patterned passivation layer further covers the gate insulating layer, the source and the drain, and the second patterned passivation layer comprises an organic insulating material.

4. The thin film transistor as claimed in claim 3, wherein the organic insulating material comprises acrylic polymer, cycloolefin polymer, epoxy resin, siloxane, fluorine polymer, or a combination thereof.

5. The thin film transistor as claimed in claim 1, wherein a thickness of the second patterned passivation layer ranges from 0.2 um to 3 um.

6. The thin film transistor as claimed in claim 1, wherein a material of the channel layer comprises IGZO, ZnO, SnO, or SnO2.

7. The thin film transistor as claimed in claim 1, wherein the channel layer is disposed between the gate insulating layer and the source and the drain.

8. The thin film transistor as claimed in claim 1, wherein a top surface of the first patterned passivation layer is lower than that of the source and drain.

9. The thin film transistor as claimed in claim 1, wherein an upper surface area of the portion of the channel layer and a lower surface area of the first patterned passivation layer have same size.