Series current limiter device

• US 8,643,055 B2
• Filed: 05/03/2010
• Issued: 02/04/2014
• Est. Priority Date: 09/26/2007
• Status: Expired due to Fees

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: STMicroelectronics NV
• Inventors: Ankoudinov, Alexei, Rodov, Vladimir, Blanchard, Richard A.
• Primary Examiner(s): Leja, Ronald W
• Application Number:
  US12/773,003
• Publication Number:
  US 20110051305A1
• Time in Patent Office: 1,373 Days
• Field of Search: 361/111, 257/124
• US Class Current: 257/124
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/423 not carrying the current to be rectified, amplified or switched
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7815 with voltage or current sensing structure, e.g. emulator section, overcurrent sensing cell
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Semiconductor protection devices, and related methods and systems, especially devices for providing series current limiting. The device typically comprises two regenerative building blocks and/or MOSFETs connected back-to-back in series, where one of the MOSFETs/Regenerative Building Blocks has an extra voltage probe electrode that provides a regenerative signal with self-limited voltage to the other via coupling to its gate electrode.

Claims

1. An apparatus comprising:

a first field effect device comprising a first source, a first drain, a first gate, and a first semiconductor region positioned in a first drift region of the first field effect device; and

a second field effect device comprising a second source, a second drain, and a second gate,

wherein the first drain is electrically connected to the second drain,

wherein;

the first source comprises a semiconductor material of a first conductivity type, and

the first semiconductor region comprises a semiconductor material of the first conductivity type.

2. The apparatus of claim 1, wherein the first drain is directly electrically connected to the second drain.

3. The apparatus of claim 1, further comprising a conductive layer electrically connected to the first drain and to the second drain.

4. The apparatus of claim 1, further comprising an electrode electrically connected to the first drain and to the second drain.

5. The apparatus of claim 1, wherein the second field effect device further comprises a second semiconductor region positioned in a second drift region of the second field effect device.

6. The apparatus of claim 1, wherein:

the first source is arranged to produce a depletion region in the first drift region when the first field effect device is in a nonconducting state, and

the first semiconductor region is positioned in the first drift region such that the first semiconductor region is within the depletion region when the first field effect device is in the nonconducting state.

7. The apparatus of claim 1, wherein the first semiconductor region is more heavily doped than the first source.

14. The apparatus of claim 1, wherein the drift region in which the first semiconductor region is positioned is a drift region to carry current between the first source and the first drain when the first field effect device is in a conducting state.

8. An apparatus comprising:

a first field effect device comprising a first source, a first drain, a first gate, and a first semiconductor region positioned in a first drift region of the first field effect device;

a second field effect device comprising a second source, a second drain, and a second gate; and

a third field effect device comprising a third source, a third drain, and a third gate, wherein the first semiconductor region of the first field effect device is electrically connected to the third gate and the first source is electrically connected to the third source,

wherein the first drain is electrically connected to the second drain.

9. The apparatus of claim 8, further comprising:

a first conductive layer electrically connected to the first semiconductor region and the third gate; and

a second conductive layer electrically connected to the first source and the third source.

10. The apparatus of claim 9, wherein:

the third field effect device comprises a third semiconductor region positioned in a third drift region of the third field effect device; and

the apparatus further comprises a third conductive layer electrically connected to the third semiconductor region and the first gate.

11. The apparatus of claim 10, wherein:

the second field effect device comprises a second semiconductor region positioned in a second drift region of the second field effect device; and

the apparatus further comprises;

a fourth field effect device comprising a fourth source, a fourth drain, a fourth gate, and a fourth semiconductor region positioned in a fourth drift region of the fourth field effect device;

a fourth conductive layer electrically connected to the second gate and to the fourth semiconductor region; and

a fifth conductive layer electrically connected to the fourth gate and to the second semiconductor region.

12. The apparatus of claim 11, further comprising:

a first external terminal electrically connected to the third drain of the third field effect device; and

a second external terminal electrically connected to the fourth drain of the fourth field effect device,

wherein the apparatus is arranged to provide to a load connected to the second external terminal protection from a surge event occurring in a circuit connected to the first external terminal.

13. The apparatus of claim 12, wherein the apparatus is a device having only two external terminals.

15. An apparatus comprising:

a first field effect device comprising a first source, a first drain, a first gate, and a first semiconductor region positioned in a first drift region of the first field effect device; and

a second field effect device comprising a second source, a second drain, and a second gate,

wherein;

the first drain is electrically connected to the second drain;

the first field effect device further comprises a body region;

the first source is positioned in the body region; and

the drift region is a portion of the body region.

16. An apparatus comprising:

a first field effect device comprising a first source, a first drain, a first gate, and a first semiconductor region positioned in a first drift region of the first field effect device; and

a second field effect device comprising a second source, a second drain, and a second gate,

wherein;

the first drain is electrically connected to the second drain;

the first field effect device further comprises a bulk region; and

the drift region is a portion of the bulk region.

17. An apparatus comprising:

a first field effect device comprising a first source, a first drain, a first gate, and a first semiconductor region positioned in a first drift region of the first field effect device;

a second field effect device comprising a second source, a second drain, a second gate, and a second semiconductor region positioned in a second drift region of the second field effect device;

a third field effect device comprising a third source, a third drain, and a third gate, wherein the first semiconductor region of the first field effect device is electrically connected to the third gate and the first source is electrically connected to the third source; and

a fourth field effect device comprising a fourth source, a fourth drain, and a fourth gate, wherein the second semiconductor region of the second field effect device is electrically connected to the fourth gate and the second source is electrically connected to the fourth source.

18. The apparatus of claim 17, wherein:

the third field effect device further comprises a third semiconductor region positioned in a third drift region of the third field effect device; and

the third semiconductor region is electrically connected to the first gate of the first field effect device.

19. The apparatus of claim 18, wherein:

the fourth field effect device further comprises a fourth semiconductor region positioned in a fourth drift region of the fourth field effect device; and

the fourth semiconductor region is electrically connected to the second gate of the second field effect device.

20. The apparatus of claim 17, wherein:

the first field effect device and the third field effect device have different channel conductivity types; and

the second field effect device and the fourth field effect device have different channel conductivity types.

21. The apparatus of claim 17, wherein:

the drain of the first field effect device is electrically connected to a first external terminal of the apparatus;

the drain of the third field effect device is electrically connected to the drain of one of the second field effect device or the fourth field effect device; and

the drain of the other of the second field effect device or the second field effect device is connected to a second external terminal of the apparatus.

22. The apparatus of claim 17, wherein:

the drain of the third field effect device is electrically connected to a first external terminal of the apparatus;

the drain of the first field effect device is electrically connected to the drain of one of the second field effect device or the fourth field effect device; and

the drain of the other of the second field effect device or the second field effect device is connected to a second external terminal of the apparatus.

23. The apparatus of claim 21 or claim 22, wherein the apparatus is arranged to provide to a load connected to the second external terminal protection from a surge event occurring in a circuit connected to the first external terminal.

24. The apparatus of claim 21 or claim 22, wherein the apparatus is a device having only two external terminals.

25. The apparatus of claim 17, further comprising:

a first device having a first conductive region and a second conductive region, the first device comprising the first field effect device and the third field effect device, the first device being arranged to conduct current in two directions, the first device having a lower voltage drop when conducting current from the first conductive region to the second conductive region than when conducting current from the second conductive region to the first conductive region; and

a second device having a third conductive region and a fourth conductive region, the second device comprising the second field effect device and the fourth field effect device, the second device being arranged to conduct current in two directions, the second device having a lower voltage drop when conducting current from the third conductive region to the fourth conductive region than when conducting current from the fourth conductive region to the third conductive region,

wherein the second conductive region is electrically connected to the fourth conductive region.

26. The apparatus of claim 25, wherein:

the drain of the first field effect device is electrically connected to the first conductive region;

the drain of the second field effect device is electrically connected to the third conductive region;

the drain of the third field effect device is electrically connected to the second conductive region; and

the drain of the fourth field effect device is electrically connected to the fourth conductive region.

27. The apparatus of claim 25, wherein the second conductive region and the fourth conductive region are portions of a same conductive region.

28. An apparatus comprising:

a first transient blocking circuit (TBC) adapted to conduct current in a first direction between a first conductive region and a second conductive region and in a second direction between the second conductive region and the first conductive region, the first TBC having a lower voltage drop in the first direction than in the second direction, the first TBC comprising a first field effect device comprising a first source, a first drain, a first gate, and a first semiconductor region disposed in a first drift region of the first field effect device; and

a second TBC adapted to conduct current in a third direction between a third conductive region and a fourth conductive region and in a fourth direction between the fourth conductive region and the third conductive region, the second TBC having a lower voltage drop in the third direction than in the fourth direction, the second TBC comprising a second field effect device comprising a second source, a second drain, a second gate, and a second semiconductor region disposed in a second drift region of the second field effect device,

wherein the second conductive region is electrically connected to the fourth conductive region, and

wherein the apparatus comprises only two external terminals, a first external terminal being electrically connected to the first conductive region and a second external terminal being electrically connected to the third conductive region.

29. The apparatus of claim 28, wherein the first drain of the first field effect device is electrically connected to the first conductive region.

30. An apparatus comprising:

a first transient blocking circuit (TBC) adapted to conduct current in a first direction between a first conductive region and a second conductive region and in a second direction between the second conductive region and the first conductive region, the first TBC having a lower voltage drop in the first direction than in the second direction, the first TBC comprising a first field effect device comprising a first source, a first drain, a first gate, and a first semiconductor region disposed in a first drift region of the first field effect device; and

a second TBC adapted to conduct current in a third direction between a third conductive region and a fourth conductive region and in a fourth direction between the fourth conductive region and the third conductive region, the second TBC having a lower voltage drop in the third direction than in the fourth direction, the second TBC comprising a second field effect device comprising a second source, a second drain, a second gate, and a second semiconductor region disposed in a second drift region of the second field effect device,

wherein;

the second conductive region is electrically connected to the fourth conductive region;

the first TBC further comprises a third field effect device, the third field effect device comprising a third source, a third drain, and a third gate, wherein the first semiconductor region of the first field effect device is electrically connected to the third gate and the first source is electrically connected to the third source; and

the second TBC further comprises a fourth field effect device, the fourth field effect device comprising a fourth source, a fourth drain, and a fourth gate, wherein the second semiconductor region of the second field effect device is electrically connected to the fourth gate and the second source is electrically connected to the fourth source;

the first field effect device and the third field effect device have different channel conductivity types; and

the second field effect device and the fourth field effect device have different channel conductivity types.

31. An apparatus comprising:

a first field effect device, the first field effect device comprising a trench, a first gate positioned in the trench, a first source positioned alongside the trench, a first drain, and a first semiconductor region positioned in a drift region of the first field effect device and alongside the trench;

a second field effect device, the second field effect device comprising a second gate, a second source, and a second drain, wherein the first semiconductor region of the first field effect device is electrically connected to the second drain; and

an electrode electrically connected to the first gate and the second drain.

32. The apparatus of claim 31, wherein the first field effect device and the second field effect device are integrated.

33. The apparatus of claim 31, further comprising an electrode electrically connected to the first source and the second source.

34. The apparatus of claim 31, wherein:

the electrode is a first electrode;

the apparatus further comprises a second electrode electrically connected to the drain; and

the first electrode and the second electrode are each connected to an external terminal of the apparatus.

35. The apparatus of claim 34, wherein the apparatus is a device having only two external terminals.

36. The apparatus of claim 31, wherein the first field effect device and the second field effect device have opposite conductivity types.

37. The apparatus of claim 31, wherein:

the second field effect device further comprises a second trench; and

the second gate is positioned in the second trench.

38. The apparatus of claim 31, wherein the drift region in which the first semiconductor region is positioned is a drift region to carry current between the first source and the first drain when the first field effect device is in a conducting state.

39. The apparatus of claim 31, wherein the first semiconductor region is arranged to produce, when the first field effect device is in a nonconducting state, a signal indicating that the first field effect device is in the nonconducting state.

40. The apparatus of claim 39, wherein the first semiconductor region is arranged to control a conductivity of the second field effect device by providing the signal to the second gate of the second field effect device.

41. The apparatus of claim 31, wherein the first field effect device is a UMOS field effect device.

53. The method of claim 41, wherein forming the third semiconductor region comprises forming the third semiconductor region adjacent to a bottom of the trench.

54. The method of claim 41, wherein forming the third semiconductor region comprises forming the third semiconductor region in a drift region of the field effect device.

55. The method of claim 54, wherein forming the third semiconductor region comprises forming the third semiconductor region in at a position that, when the field effect device is in a non-conducting state, will be in a depletion region of the field effect device.

42. An apparatus comprising:

a first field effect device, the first field effect device comprising a trench, a first gate positioned in the trench, a first source positioned alongside the trench, a first drain, and a first semiconductor region positioned in a drift region of the first field effect device and alongside the trench; and

a second field effect device, the second field effect device comprising a second gate, a second source, and a second drain, wherein the first semiconductor region of the first field effect device is electrically connected to the second drain,

wherein;

the first field effect device further comprises a body region;

the first source is positioned in the body region; and

the drift region is a portion of the body region.

43. An apparatus comprising:

a first field effect device, the first field effect device comprising a trench, a first gate positioned in the trench, a first source positioned alongside the trench, a first drain, and a first semiconductor region positioned in a drift region of the first field effect device and alongside the trench; and

a second field effect device, the second field effect device comprising a second gate, a second source, and a second drain, wherein the first semiconductor region of the first field effect device is electrically connected to the second drain,

wherein;

the first field effect device further comprises a bulk region; and

the drift region is a portion of the bulk region.

44. A method of producing a field effect device, comprising:

forming a trench in a first semiconductor region;

forming a gate insulator in the trench;

forming a gate in the trench;

forming a first conduction terminal for the field effect device in the first semiconductor region adjacent to the trench, the first conduction terminal comprising a semiconductor material of a first conductivity type;

forming a second conduction terminal for the field effect device at a position separated from the trench by a portion of the first semiconductor region, the second conduction terminal comprising a semiconductor material of the first conductivity type; and

forming a third semiconductor region of the first conductivity type alongside the trench and in the first semiconductor region.

45. The method of claim 44, wherein forming the third semiconductor region of the first conductivity type comprises forming the third semiconductor region at a position separated from the gate by the gate insulator.

46. The method of claim 44, further comprising forming a second field effect device integrated with the field effect device, wherein forming the second field effect device comprises:

forming a second gate for the second field effect device;

forming a third conduction terminal for the second field effect device in the first semiconductor region, the third conduction terminal comprising a semiconductor material of a second conductivity type different from the first conductivity type; and

forming a fourth conduction terminal for the second field effect device in the first semiconductor region, the fourth conduction terminal comprising a semiconductor material of the second conductivity type.

47. The method of claim 46, wherein the first semiconductor region is an epitaxial layer.

48. The method of claim 46, further comprising forming a conductive region electrically connecting the third semiconductor region to the second gate for the second field effect device.

49. The method of claim 46, wherein forming the gate insulator in the trench comprises forming an insulator region to act as the gate insulator of the field effect device and the gate insulator of the second field effect device.

50. The method of claim 46, wherein forming the second gate comprises:

forming a second trench in the first semiconductor region; and

forming the second gate in the second trench.

51. The method of claim 46, further comprising forming a conductive region electrically connecting the third conduction terminal and the first conduction terminal.

52. The method of claim 46, wherein:

forming the first conduction terminal comprises forming a source of the field effect device;

forming the second conduction terminal comprises forming a drain of the field effect device;

forming the third conduction terminal comprises forming a source of the first field effect device; and

forming the fourth conduction terminal comprises forming a drain of the second field effect device.