Integrated circuit having field effect transistors and manufacturing method

• US 8,643,068 B2
• Filed: 03/12/2009
• Issued: 02/04/2014
• Est. Priority Date: 03/12/2009
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Meyer, Thorsten, Decker, Stefan, Krischke, Norbert, Kadow, Christoph
• Primary Examiner(s): Le, Thao
• Assistant Examiner(s): PARKER, ALLEN L
• Application Number:
  US12/402,943
• Publication Number:
  US 20100230764A1
• Time in Patent Office: 1,790 Days
• Field of Search: 257/101, 257/285, 257/219, 257/221, 257/E29.012
• US Class Current: 257/285
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66537 using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

An integrated circuit having field effect transistors and manufacturing method. One embodiment provides an integrated circuit including a first FET and a second FET. At least one of source, drain, gate of the first FET is electrically connected to the corresponding one of source, drain, gate of the second FET. At least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET are connected to a circuit element, respectively. A dopant concentration of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel.

Claims

1. An integrated circuit, comprising:

a first FET and

a second FET,

wherein

the first FET is a power FET and

the second FET

is a sense FET

having an area that is smaller than the area of the power FET,

wherein

at least one of a source, drain, or gate of the first FET is electrically connected to the corresponding one of a source, drain, or gate of the second FET,

at least one further of the source, drain, or gate of the first FET and the corresponding one further of the source, drain, or gate of the second FET are connected to a circuit element, respectively; and

a dopant concentration profile of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel,

wherein a value of the dopant concentration profile of the body at the peak location of each of the first and second FETs is larger or at least equal to any value of the dopant concentration profile of the body in an extension region that extends into the source,

wherein the dopant concentration profile of the body of the first FET and the dopant concentration profile of the body of the second FET follow substantially similar contours along the channel of the first and second FETs respectively.

2. The integrated circuit of claim 1, wherein the dopant concentration profile of the body of each of the first and second FETs is declining along the channel from the peak location to a pn junction between the body and source.

3. The integrated circuit of claim 1,

wherein the dopant concentration profile of the body of each of the first and second FETs is constant along the channel between a pn junction between body and source and the peak location within the channel, the dopant concentration profile declining from the peak location to the drain.

4. The integrated circuit of claim 1, wherein a fraction of a channel area of each of the first and second FETs having a dopant concentration of the body of at least 95% of a value at the peak location to an overall channel area of the respective FET is at least 15%.

5. The integrated circuit of claim 1,

wherein the dopant concentration profile of the body of each of the first and second FETs has multiple peaks along the channel.

6. The integrated circuit of claim 5, wherein the multiple peaks have a same maximum dopant concentration.

7. The integrated circuit of claim 1,

wherein the dopant concentration profile of the body of each of the first and second FETs has a single peak within the channel, the dopant concentration profile of the body declining to both ends of the channel in the direction of source and drain.

8. The integrated circuit of claim 1,

wherein the gate of the first FET is connected to the gate of the second FET;

one of the source and drain of the first FET is connected to the corresponding one of the source and drain of the second FET; and

wherein the other one of the source and drain of the first FET and the other one of the source and drain of the second FET are connected to the circuit element.

9. The integrated circuit of claim 1,

wherein the dopant concentration profile of the body of each of the first and second FETs continuously declines within the source.

10. An integrated circuit, comprising:

a first FET and

a second FET,

wherein

the first FET is a power FET and

the second FET

is a sense FET

having an area that is smaller than the area of the power FET,

wherein at least one of a source, drain, or gate of the first FET is electrically connected to the corresponding one of a source, drain, or gate of the second FET,

wherein at least one further of the source, drain, or gate of the first FET and the corresponding one further of the source, drain, or gate of the second FET are connected to a circuit element respectively,

wherein

a dopant concentration profile of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel,

the dopant concentration profile declining along the channel from the peak location to a pn junction between the body and source of the first and second FETs respectively, and

wherein a value of the dopant concentration profile of the body at the peak location of each of the first and second FETs is larger or at least equal to any value of the dopant concentration profile of the body in an extension region that extends into the source; and

wherein the dopant concentration profile of the body of the first FET and the dopant concentration profile of the body of the second FET follow substantially similar contours along the channel of the first and second FETs respectively.

11. The integrated circuit of claim 10,

wherein the dopant concentration profile of the body of each of the first and second FETs has multiple peaks along the channel.

12. The integrated circuit of claim 10,

wherein the dopant concentration profile of the body of each of the first and second FETs has a single peak within the channel, the dopant concentration profile of the body declining to both ends of the channel in the direction of the source and drain.

13. The integrated circuit of claim 10, wherein a fraction of a channel area of each of the first and second FETs having a dopant concentration of the body of at least 95% of a value at the peak location to an overall channel area of the respective FET is at least 15%.

14. The integrated circuit of claim 10,

wherein the gate of the first FET is connected to the gate of the second FET;

one of the source and drain of the first FET is connected to the corresponding one of the source and drain of the second FET; and

wherein the other one of the source and drain of the first FET and the other one of the source and drain of the second FET are connected to the circuit element.

15. An integrated circuit, comprising:

a first FET and

a second FET,

wherein

the first FET is a power FET and

the second FET

is a sense FET

having an area that is smaller than the area of the power FET,

wherein

at least one of a source, drain, or gate of the first FET is electrically connected to the corresponding one of a source, drain, or gate of the second FET,

at least one further of the source, drain, or gate of the first FET and the corresponding one further of the source, drain, or gate of the second FET are connected to a circuit element, respectively; and

a dopant concentration profile of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel,

wherein

at an intersection of the dopant concentration profile of the body and a profile of the dopant concentration of the source of each of the first and second FETs,

the dopant concentration profile of the body declines into the source and

the profile of the dopant concentration of the source declines into the body,

wherein a the dopant concentration profile of the body of the first FET and the dopant concentration profile of the body of the second FET follow substantially similar contours along the channel of the first and second FETs respectively.

16. The integrated circuit of claim 15,

wherein the dopant concentration profile of the body of each of the first and second FETs is declining along the channel from the peak location to a pn junction between the body and source.

17. The integrated circuit of claim 15, wherein a fraction of a channel area of each of the first and second FETs having a dopant concentration of the body of at least 95% of a value at the peak location to an overall channel area of the respective FET is at least 15%.

18. The integrated circuit of claim 15,

wherein the dopant concentration profile of the body of each of the first and second FETs has a single peak within the channel,

the dopant concentration profile of the body declining to both ends of the channel in the direction of the source and drain.

19. The integrated circuit of claim 15,

wherein the gate of the first FET is connected to the gate of the second FET;

one of the source and drain of the first FET is connected to the corresponding one of the source and drain of the second FET; and

wherein the other one of the source and drain of the first FET and the other one of the source and drain of the second FET are connected to the circuit element.

20. An integrated circuit, comprising:

a first FET and a second FET,

wherein

the first FET is a power FET and

the second FET

is a sense FET

having an area that is smaller than the area of the power FET,

wherein at least one of a source, drain, or gate of the first FET is electrically connected to the corresponding one of a source, drain, or gate of the second FET, and

wherein at least one further of the source, drain, gate of the first FET and the corresponding one further of the source, drain, gate of the second FET are connected to a circuit element, respectively;

wherein

a dopant concentration profile of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel,

the dopant concentration profile declining along the channel from the peak location to a pn junction between body and source, and

wherein

at an intersection of the dopant concentration profile of the body and a profile of the dopant concentration of the source of each of the first and second FETs,

the dopant concentration profile of the body declines into the source and

the profile of the dopant concentration of the source declines into the body, and

wherein the dopant concentration profile of the body of the first FET and the dopant concentration profile of the body of the second FET follow substantially similar contours along the channel of the first and second FETs respectively.

21. The integrated circuit of claim 20,

wherein the dopant concentration profile of the body of each of the first and second FETs has a single peak within the channel,

the dopant concentration profile of the body declining to both ends of the channel in the direction of the source and drain.