Trench-gate metal oxide semiconductor device and fabricating method thereof

• US 8,643,097 B2
• Filed: 08/09/2011
• Issued: 02/04/2014
• Est. Priority Date: 08/09/2011
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Liu, Kuan-Ling, Ueng, Shih-Yuan
• Primary Examiner(s): Nguyen, Dao H
• Application Number:
  US13/205,767
• Publication Number:
  US 20130037880A1
• Time in Patent Office: 910 Days
• Field of Search: 257/270, 257/330, 257/331, 257/342, 257/E21.41, 257/E29.262, 438/341, 438/386, 438/488
• US Class Current: 257/331
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/6634 with a recess formed by etching in the source/emitter contact region H01L29/66348 takes precedence; etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/10253 Silicon [Si]

Abstract

A trench-gate metal oxide semiconductor device includes a substrate, a first gate dielectric layer, a first gate electrode and a first source/drain structure. The substrate has a first doping region, a second doping region and at least one trench. A P/N junction is formed between the first doping region and the second doping region. The trench extends from a surface of the substrate to the first doping region through the second doping region and the P/N junction. The first gate dielectric layer is formed on a sidewall of the second trench. The first gate electrode is disposed within the trench. A height difference between the top surface of the first gate electrode and the surface of the substrate is substantially smaller than 1500 Å. The first source/drain structure is formed in the substrate and adjacent to the first gate dielectric layer.

Claims

1. A trench-gate metal oxide semiconductor device, comprising:

a substrate having a first doping region, a second doping region and at least one trench, wherein a P/N junction is formed between the first doping region and the second doping region, and the trench extends from a surface of the substrate to the first doping region through the second doping region and the P/N junction;

a first gate dielectric layer formed on a sidewall of the trench;

a first gate electrode disposed within the trench and having a top surface, wherein the top surface of the first gate electrode is lower than the surface of the substrate, a height difference between the top surface of the first gate electrode and the surface of the substrate is substantially smaller than 1500 Å

; and

a first source/drain structure formed in the substrate and adjacent to the first gate dielectric layer.

2. The trench-gate metal oxide semiconductor device according to claim 1, further comprising a dielectric capping layer for covering the top surface of the first gate electrode.

3. The trench-gate metal oxide semiconductor device according to claim 1, wherein the first doping region is an N-type well region extending from the surface of the substrate into the substrate, and the second doping region is a P-type well region extending from the surface of the substrate to the N-type well region.

4. The trench-gate metal oxide semiconductor device according to claim 3, wherein the substrate further comprises:

an N-type buried layer; and

a P-type epitaxial layer formed over the buried layer, wherein the N-type well region extends from the surface of the substrate to the P-type epitaxial layer.

5. The trench-gate metal oxide semiconductor device according to claim 3, wherein the first source/drain structure is an N-type doping structure extending from the surface of the substrate to the P-type well region along the sidewall of the trench.

6. The trench-gate metal oxide semiconductor device according to claim 1, further comprising:

a third doping region formed in the substrate and separated from the first doping region, wherein the third doping region and the first doping region have the same polarity;

a second gate dielectric layer formed on the surface of the substrate corresponding to the third doping region;

a second gate electrode formed on the second gate dielectric layer; and

a second source/drain structure formed in the third doping region and adjacent to the second gate dielectric layer, wherein the second source/drain structure and the second doping region have the same polarity.