Method of making a semiconductor structure useful in making a split gate non-volatile memory cell
First Claim
1. A method of making a semiconductor device comprising:
- forming a select gate dielectric layer over a semiconductor substrate;
forming a select gate layer over the select gate dielectric layer;
forming a select gate sidewall of the select gate layer and the select gate dielectric layer by removing at least a portion of the select gate layer and the select gate dielectric layer, whereinsaid removing further results in exposing a surface of the semiconductor substrate;
forming a charge storage stack over at least a portion of the exposed surface of the semiconductor substrate and at least a portion of the select gate sidewall, whereina corner portion of a top surface of the charge storage stack is non-conformal with a corner region between the select gate sidewall and the exposed surface of the semiconductor substrate,the charge storage stack comprises;
a first to dielectric layer over a charge storage layer; and
a second to dielectric layer over the first to dielectric layer, the second to dielectric layer is non-conformal with the first to dielectric layer, andthe corner portion of the top surface of the charge storage stack has a radius of curvature measuring approximately one-third of a thickness of the charge storage stack over the substrate surface or greater; and
forming a control gate layer over the charge storage stack.
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Accused Products
Abstract
A semiconductor device comprises a semiconductor substrate and a select gate structure over a first portion of the semiconductor substrate. The select gate structure comprises a sidewall forming a corner with a second portion of the semiconductor substrate and a charge storage stack over an area comprising the second portion of the semiconductor substrate, the sidewall, and the corner. A corner portion of a top surface of the charge storage stack is non-conformal with the corner, and the corner portion of the top surface of the charge storage stack has a radius of curvature measuring approximately one-third of a thickness of the charge storage stack over the second portion of the substrate or greater. A control gate layer is formed over the charge storage stack. A portion of the control gate layer conforms to the corner portion of the top surface of the charge storage stack.
11 Citations
20 Claims
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1. A method of making a semiconductor device comprising:
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forming a select gate dielectric layer over a semiconductor substrate; forming a select gate layer over the select gate dielectric layer; forming a select gate sidewall of the select gate layer and the select gate dielectric layer by removing at least a portion of the select gate layer and the select gate dielectric layer, wherein said removing further results in exposing a surface of the semiconductor substrate; forming a charge storage stack over at least a portion of the exposed surface of the semiconductor substrate and at least a portion of the select gate sidewall, wherein a corner portion of a top surface of the charge storage stack is non-conformal with a corner region between the select gate sidewall and the exposed surface of the semiconductor substrate, the charge storage stack comprises; a first to dielectric layer over a charge storage layer; and a second to dielectric layer over the first to dielectric layer, the second to dielectric layer is non-conformal with the first to dielectric layer, and the corner portion of the top surface of the charge storage stack has a radius of curvature measuring approximately one-third of a thickness of the charge storage stack over the substrate surface or greater; and forming a control gate layer over the charge storage stack. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A semiconductor device comprising:
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a semiconductor substrate; a select gate structure over a first portion of the semiconductor substrate, wherein the select gate structure comprises a sidewall forming a corner with a second portion of the semiconductor substrate; a charge storage stack over an area comprising the second portion of the semiconductor substrate, the sidewall, and the corner, wherein the charge storage stack comprises; a bottom dielectric layer over the sidewall and the surface of the second portion of the semiconductor substrate; a charge storage layer over the bottom dielectric layer; and a to dielectric layer over the charge storage layer, the to dielectric layer comprises; a first top dielectric layer over the charge storage layer; and a second top dielectric layer over the first top dielectric layer; a corner portion of a top surface of the charge storage stack is non-conformal with the first top dielectric layer and the corner, and the corner portion of the top surface of the charge storage stack has a radius of curvature greater than or equal to one-third of a thickness of the charge storage stack over the second portion of the substrate or greater; and a control gate layer over the charge storage stack, wherein a portion of the control gate layer conforms to the corner portion of the top surface of the charge storage stack. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification