Pads and pin-outs in three dimensional integrated circuits

• US 8,643,162 B2
• Filed: 11/19/2007
• Issued: 02/04/2014
• Est. Priority Date: 11/19/2007
• Status: Active Grant

• Current Assignee: Liberty Patents LLC
• Original Assignee: Callahan Cellular LLC (Intellectual Ventures LLC)
• Inventors: Madurawe, Raminda Udaya
• Primary Examiner(s): Dickey, Thomas L
• Application Number:
  US11/986,023
• Publication Number:
  US 20090146189A1
• Time in Patent Office: 2,269 Days
• Field of Search: 257/209, 257/686, 257/E21.614, 257/E21.703, 257/E27.026, 326/41, 438/202
• US Class Current: 257/686
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 27/118 Masterslice integrated circuits
• CPC Class Codes: H01L 27/11803 using field effect technology
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A three dimensional semiconductor device, comprising: a substrate including a plurality of circuits; a plurality of pads, each pad coupled to a said circuit; and a memory array positioned above or below the substrate coupled to a said circuit to program the memory array.

Claims

1. A semiconductor device, comprising:

a first layer including a configuration circuit;

a second layer including a plurality of circuits; and

a third layer including a plurality of pads, wherein the configuration circuit is configured to be dependent on at least one of the plurality of circuits to access information from an external source through the plurality of pads, wherein the configuration circuit is operable to use the information to configure at least one of the plurality of circuits, and wherein the first layer, the second layer, and the third layer form a stack.

2. The semiconductor device of claim 1, wherein the plurality of circuits comprise an input/output circuit.

3. The semiconductor device of claim 1, wherein the configuration circuit comprises one of:

a field-programmable memory array or a mask-programmable metal pattern.

4. The semiconductor device of claim 1, wherein the plurality of pads are coupled to pins of a package.

5. The semiconductor device of claim 1, wherein the plurality of pads are positioned along a perimeter of the third layer.

6. The semiconductor device of claim 1, wherein the plurality of circuits comprise an input buffer circuit operable to receive the information from at least one of the plurality of pads and to send the information to the configuration circuit.

7. The semiconductor device of claim 1, wherein the configuration circuit comprises at least one of:

a fuse, an antifuse, a SRAM cell, a DRAM cell, a metal optional link, an EPROM, an EEPROM, a flash cell, a resistance modulating element, a magneto-electric element, a photo-electric element, or a ferro-electric element.

8. The semiconductor device of claim 1, wherein the plurality of circuits comprise a driver circuit operable to write the information in the configuration circuit and a sense amplifier circuit operable to read the information from the configuration circuit.

9. The semiconductor device of claim 1, wherein the configuration circuit comprises a memory array, and wherein the first layer further comprises a driver circuit operable to write the information in the memory array and a sense amplifier circuit operable to read the information from the memory array.

10. The semiconductor device of claim 1, wherein the plurality of circuits comprise a circuit configured to request the information from the external source through at least one of the plurality of pads at power-up.

11. A method, comprising:

forming a stack comprising a first layer including a configuration circuit, a second layer including a plurality of circuits, and a third layer including a plurality of pads; and

coupling a portion of the plurality of circuits to the plurality of pads, wherein the configuration circuit is configured to be dependent on at least one of the plurality of circuits to access information from an external source through the pads, and wherein the configuration circuit is operable to use the information to configure at least one of the plurality of circuits.

12. The method of claim 11, wherein the plurality of circuits comprise an input/output circuit.

13. The method of claim 11, wherein said forming a stack comprises:

forming the plurality of pads along a perimeter of the third layer.

14. The method of claim 11, wherein in a field-programmable gate array (FPGA) configuration, the configuration circuit comprises a field-programmable memory array.

15. The method of claim 11, wherein in an application-specific integrated circuit (ASIC) configuration, the configuration circuit comprises a mask-programmable metal pattern.

16. The method of claim 11, wherein said forming a stack comprises:

depositing thin film transistors on the first layer.

17. The method of claim 11, wherein the stack further comprises a substrate.

18. A semiconductor device, comprising:

a substrate including a plurality of circuits;

a first layer including a configuration circuit; and

a second layer including a plurality of pads, wherein the configuration circuit is configured to be dependent on at least one of the plurality of circuits to access information from an external source through the pads, wherein the configuration circuit is operable to use the information to configure at least one of the plurality of circuits, and wherein the substrate, the first layer, and the second layer form a stack.

19. The semiconductor device of claim 18, wherein the configuration circuit comprises a memory array.

20. The semiconductor device of claim 19, wherein the plurality of circuits comprise a driver circuit operable to write the information in the memory array and a sense amplifier circuit operable to read the information from the memory array.