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Pads and pin-outs in three dimensional integrated circuits

  • US 8,643,162 B2
  • Filed: 11/19/2007
  • Issued: 02/04/2014
  • Est. Priority Date: 11/19/2007
  • Status: Active Grant
First Claim
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1. A semiconductor device, comprising:

  • a first layer including a configuration circuit;

    a second layer including a plurality of circuits; and

    a third layer including a plurality of pads, wherein the configuration circuit is configured to be dependent on at least one of the plurality of circuits to access information from an external source through the plurality of pads, wherein the configuration circuit is operable to use the information to configure at least one of the plurality of circuits, and wherein the first layer, the second layer, and the third layer form a stack.

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