Processed wafer via

• US 8,643,186 B2
• Filed: 07/29/2010
• Issued: 02/04/2014
• Est. Priority Date: 06/14/2005
• Status: Active Grant

• Current Assignee: Cufer Asset Ltd LLC (Intellectual Ventures LLC)
• Original Assignee: Cufer Asset Ltd LLC (Intellectual Ventures LLC)
• Inventors: Trezza, John
• Primary Examiner(s): Tran, Long K
• Assistant Examiner(s): Tran, Dzung
• Application Number:
  US12/846,495
• Publication Number:
  US 20100304565A1
• Time in Patent Office: 1,286 Days
• Field of Search: 257/773, 257/233, 257/465, 257/698, 438105-108, 438/207
• US Class Current: 257/773
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2223/6616 Vertical connections, e.g. vias
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05023 the whole internal layer protruding from the surface
• CPC Class Codes: H01L 2224/05026 the internal layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05027 the internal layer extending out of an opening
• CPC Class Codes: H01L 2224/0508 being stacked
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05664 : Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/05666 : Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/0615 : Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
• CPC Class Codes: H01L 2224/1147 : using a lift-off mask
• CPC Class Codes: H01L 2224/13012 : in top view
• CPC Class Codes: H01L 2224/13099 : Material
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13609 : Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/16 : of an individual bump connector
• CPC Class Codes: H01L 2224/75305 : comprising protrusions
• CPC Class Codes: H01L 2224/81193 : wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/8121 : using a reflow oven
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06524 : Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06527 : Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06589 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 2225/06593 : Mounting aids permanently on device; arrangements for alignment use of temporary supports H01L21/6835
• CPC Class Codes: H01L 2225/06596 : Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 23/427 : Cooling by change of state, e.g. use of heat pipes by liquefied gas H01L23/445
• CPC Class Codes: H01L 23/48 : Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/552 : Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/75 : Apparatus for connecting with bump connectors or layer connectors
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01025 : Manganese [Mn]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01051 : Antimony [Sb]
• CPC Class Codes: H01L 2924/01061 : Promethium [Pm]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: Y10T 428/24174 : including sheet or component perpendicular to plane of web or sheet

Abstract

An apparatus involves a semiconductor wafer that has been back-end processed, the semiconductor wafer including a substrate, electronic devices and multiple metalization layers, a via extending from an outer surface of the substrate through the substrate to a metalization layer from among the multiple metalization layers, and an electrically conductive material within the via, the electrically conductive material forming an electrically conductive path from the metalization layer to the outer surface. A method of processing a semiconductor wafer that has been front-end and back-end processed involves forming a via in the semiconductor wafer extending from a surface of the wafer, into and through semiconductor material, to a metalization layer formed during the back-end processing by etching the semiconductor wafer; and making the via electrically conductive so as to form an electrical path within the via extending from the surface of the wafer to the metalization layer.

Claims

1. A method comprising:

forming a via in a semiconductor material, wherein the via extends from a surface of the semiconductor material to a metalization layer formed during back-end processing; and

depositing an electrically-conductive material within the via to form an electrically-conductive path between the surface of the semiconductor material and the metalization layer.

2. The method of claim 1, wherein said forming a via in a semiconductor material is performed after the back-end processing.

3. The method of claim 1, wherein said forming a via in a semiconductor material comprises etching an annular via in the semiconductor material.

4. The method of claim 1, wherein said forming a via in a semiconductor material further comprises creating an island of semiconductor material within a semiconductor wafer.

5. The method of claim 4, wherein said forming a via in a semiconductor material further comprises removing at least a portion of the island of semiconductor material.

6. The method of claim 1, wherein said depositing an electrically-conductive material within the via comprises creating a coaxial conductor within the via, and wherein the coaxial conductor includes dual electrically-isolated conductors.

7. The method of claim 1, wherein said forming a via in a semiconductor material comprises etching an annular via in the semiconductor material, wherein said depositing an electrically-conductive material within the via further comprises depositing the electrically-conductive material on inner and outer sidewalls of the annular via, and wherein the method further comprises thinning the semiconductor material until the electrically-conductive material deposited on the inner sidewalls is electrically isolated from the electrically-conductive material deposited on the outer sidewalls.

8. The method of claim 1, wherein said depositing an electrically-conductive material within the via comprises creating a triaxial conductor within the via, and wherein the triaxial conductor includes three electrically-isolated conductors.

9. The method of claim 1, further comprising, prior to said depositing an electrically-conductive material within the via, applying an electrically-insulative material to a surface of the via.

10. The method of claim 1, further comprising forming devices in a front-end process on the semiconductor material, wherein the devices are electrically connected by the metalization layer.

11. The method of claim 1, wherein the back-end processing comprises adding metalization layers to create electrically-conductive paths that are configured to electrically connect to on-chip devices on a separate front-end processed semiconductor wafer.

12. A method comprising:

performing back-end processing on a semiconductor wafer to form at least one metalization layer;

forming a via in the semiconductor wafer that extends between a surface of the semiconductor wafer and the at least one metalization layer; and

depositing an electrically-conductive material within the via to form an electrically-conductive path between the surface of the semiconductor wafer and the at least one metalization layer.

13. The method of claim 12, wherein the at least one metalization layer is configured to electrically connect devices formed during front-end processing.

14. The method of claim 13, further comprising forming devices in a front-end process on another semiconductor wafer and connecting the other semiconductor wafer to the semiconductor wafer such that the devices are electrically connected by the at least one metalization layer.

15. The method of claim 12, wherein said performing back-end processing comprises forming a plurality of metalization layers.

16. The method of claim 15, wherein said forming a via in the semiconductor wafer comprises forming the via in the semiconductor wafer such that it extends from the surface of the semiconductor wafer to an internal metalization layer of the plurality of metalization layers.

17. The method of claim 12, wherein said forming a via in the semiconductor wafer comprises etching an annular via in the semiconductor material, and wherein the annular via surrounds an island of semiconductor material.

18. The method of claim 17, further comprising removing at least a portion of the island of semiconductor material.

19. The method of claim 17, wherein said depositing an electrically-conductive material within the via creates a coaxial conductor within the via, and wherein the coaxial conductor includes dual electrically-isolated conductors.

20. The method of claim 17, wherein said depositing an electrically-conductive material within the via comprises depositing the electrically-conductive material on inner and outer sidewalls of the annular via, and wherein the method further comprises thinning the semiconductor wafer until the electrically-conductive material deposited on the inner sidewalls is electrically isolated from the electrically-conductive material deposited on the outer sidewalls.

21. The method of claim 12, wherein said depositing an electrically-conductive material within the via comprises creating a triaxial conductor within the via, and wherein the triaxial conductor includes three electrically-isolated conductors.

22. The method of claim 12, further comprising thinning a substrate of the semiconductor wafer prior to said forming a via in the semiconductor wafer.

23. The method of claim 12, further comprising, prior to said depositing an electrically-conductive material within the via, applying an electrically-insulative material to a surface of the via.

24. The method of claim 14, wherein during said connecting the other semiconductor wafer to the semiconductor wafer, the other semiconductor wafer has not been back-end processed and the semiconductor wafer has not been front-end processed.

25. A method comprising:

performing back-end processing on a semiconductor wafer;

forming a via in the semiconductor wafer after completion of the back-end processing;

depositing a first electrically-conductive material within the via to form an electrically-conductive path within the via.

26. The method of claim 25, wherein said performing back-end processing comprises forming a plurality of metalization layers.

27. The method of claim 26, wherein said forming a via in the semiconductor wafer comprises forming the via in the semiconductor wafer such that it extends from the surface of the semiconductor wafer to one of the plurality of metalization layers.

28. The method of claim 25, wherein said forming a via in the semiconductor wafer comprises etching an annular via in the semiconductor wafer, and wherein the annular via surrounds an island of semiconductor material.

29. The method of claim 28, wherein said depositing a first electrically-conductive material within the via comprises depositing the first electrically-conductive material on inner and outer sidewalls of the annular via, and wherein the method further comprises thinning the semiconductor wafer until the first electrically-conductive material deposited on the inner sidewalls is electrically isolated from the first electrically-conductive material deposited on the outer sidewalls.

30. The method of claim 28, further comprising, prior to said depositing a first electrically-conductive material within the via, applying an electrically-insulative material to an inner sidewall of the via.

31. The method of claim 28, further comprising removing the island of semiconductor material and depositing a second electrically-conductive material within a space vacated by the island of semiconductor material to form a coaxial conductor, wherein the coaxial conductor includes the second electrically-conductive material electrically isolated from the first electrically-conductive material.

32. The method of claim 25, further comprising thinning a substrate of the semiconductor wafer prior to said forming a via in the semiconductor wafer.