Level shifter circuit

• US 8,643,425 B2
• Filed: 09/19/2011
• Issued: 02/04/2014
• Est. Priority Date: 09/19/2011
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Chaudhry, Nidhi, Sharma, Parul K., Srivastava, Amit K.
• Primary Examiner(s): Donovan, Lincoln
• Assistant Examiner(s): CHENG, DIANA
• Application Number:
  US13/235,499
• Publication Number:
  US 20130069707A1
• Time in Patent Office: 869 Days
• Field of Search: 327/306, 327/333, 326 62- 64, 326/68, 326/80, 326/81
• US Class Current: 327/333
• CPC Class Codes: H03K 3/356182 with additional means for controlling the main nodes

Abstract

An embedded system includes a level shifter circuit for generating a forward supply voltage level in a predefined range. A sense circuit senses a core supply voltage level of the embedded system and compares the sensed core supply voltage level with a predetermined minimum core supply voltage level needed to generate the forward supply voltage. A reset circuit maintains one or more input nodes and one or more internal nodes of the level shifter circuit at a predetermined voltage level when the core supply voltage level is less than the predetermined minimum core supply voltage level.

Claims

1. A method for operating a level shifter circuit to maintain forward supply voltage levels in predefined ranges, the method comprising:

sensing a core supply voltage level;

comparing the sensed core supply voltage level with a predefined core supply voltage level needed to ensure voltage level shifting at an output of the level shifter circuit;

maintaining one or more input nodes and one or more internal nodes of the level shifter circuit at a predetermined voltage level when the sensed core supply voltage level is below the predefined core supply voltage level;

operating the level shifter circuit using a transistor pair connected as a differential amplifier; and

protecting the transistor pair with a pair of protection transistors, wherein the protection transistors receive an input from at least one of the one or more input nodes, and wherein gates of the protection transistor pair are biased within a predefined voltage difference from the core supply voltage level.

2. The method of claim 1, wherein maintaining the one or more input nodes and one or more internal nodes of the level shifter circuit at the predetermined voltage level comprises maintaining the one or more input nodes at a predetermined low voltage level.

3. An embedded system for maintaining forward supply voltage levels in predefined ranges, the embedded system comprising:

a level shifter circuit that generates one or more forward supply voltage levels in predefined ranges, the level shifter circuit comprising one or more input nodes, one or more internal nodes, one or more output nodes, and a common ground node;

a sense circuit for sensing a core supply voltage level of the embedded system and comparing the sensed core supply voltage level with a predetermined core supply voltage level that is needed to ensure voltage level shifting at the output nodes of the level shifter circuit;

a reset circuit that maintains the one or more input nodes and one or more internal nodes of the level shifter circuit at a predetermined voltage level when the core supply voltage level is less than the predetermined core supply voltage level; and

a protection transistor pair that receive an input from at least one of the one or more input nodes, and wherein gates of the protection transistor pair are biased within a predefined voltage difference from the core supply voltage level.

4. The embedded system of claim 3, wherein the reset circuit comprises a pair of first voltage limiting devices that receive an input signal from the sense circuit, and wherein each of the pair of first voltage limiting devices is connected to the common ground node.

5. The embedded system of claim 4, wherein the first voltage limiting devices comprise one of a PMOS field effect transistor, an NMOS field effect transistor, a CMOS transistor, and a bipolar junction transistor.

6. The embedded system of claim 4, wherein the level shifter circuit further comprises a plurality of second voltage limiting devices, wherein the plurality of second voltage limiting devices protect the internal nodes from exceeding a predefined reliability limit.

7. The embedded system of claim 6, wherein each of the plurality of second voltage limiting devices is one of a PMOS field effect transistor, an NMOS field effect transistor, a CMOS transistor and a bipolar junction transistor.

8. The embedded system of claim 3, wherein the level shifter circuit further comprises a transistor pair connected as a differential amplifier.

9. The embedded system of claim 8, wherein the level shifter circuit further comprises an inverter having an input node and an output node connected to each of the transistors of the transistor pair.

10. The embedded system of claim 3, wherein the sense circuit comprises a comparator for comparing the core supply voltage level with the predetermined minimum core supply voltage level.