Voltage level shifter

• US 8,643,426 B2
• Filed: 09/06/2012
• Issued: 02/04/2014
• Est. Priority Date: 02/28/2012
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Zhang, Wenzhong, Guo, Yin, Zhang, Shayan
• Primary Examiner(s): O NEILL, PATRICK
• Application Number:
  US13/605,987
• Publication Number:
  US 20130222037A1
• Time in Patent Office: 516 Days
• Field of Search: 327/333, 326/62, 326/63, 326/80, 326/81
• US Class Current: 327/333
• CPC Class Codes: H03K 3/356182 with additional means for controlling the main nodes

Abstract

A voltage level shifter has an input circuit with an inverter coupled to an input node, a pull-down control transistor with a gate coupled to a first node of the inverter, and a pull-up control transistor with a gate coupled to a second node of the inverter. Sources of the pull-down and pull-up control transistors are coupled to a low voltage reference. A transient connectivity limiter (TCL) has pull-down and pull-up transistors. Two control inputs are coupled to respective first and second nodes of the inverter and path inputs are coupled to respective drains of the pull-down and pull-up control transistors. An output circuit has inputs coupled to pull-up and pull-down nodes of the TCL. During a voltage level transition at the input node, the TCL connects the pull-up node to the low voltage reference through the TCL pull-up transistor transitioning from a saturation to a sub-threshold region of operation.

Claims

1. A voltage level shifter, comprising:

an input node and an output node;

an input circuit with an input inverter coupled to the input node, wherein the input circuit has a pull-down transistor with a gate electrode coupled to a first node of the input inverter and a first pull-up control transistor with a gate electrode coupled to an opposite second node of the input inverter, and wherein source electrodes of the pull-down transistor and the first pull-up control transistor are coupled to a low voltage reference;

a transient path connectivity limiter with a pull-down transient connectivity limiter transistor and a pull-up transient connectivity limiter transistor, wherein the pull-down transient connectivity limiter transistor has a gate electrode coupled through a first capacitor to the first node of the input inverter and a source electrode of the pull-down transient connectivity limiter transistor is coupled to a drain electrode of the pull-down transistor, and wherein the pull-up transient connectivity limiter transistor has a gate electrode coupled through a second capacitor to the second node of the input inverter and a source electrode of the pull-up transient connectivity limiter transistor is coupled to a drain electrode of the first pull-up control transistor, wherein the transient path connectivity limiter further includes a rapid response pull-down gate control transistor having a source electrode coupled to the gate electrode of the pull-down transient connectivity limiter transistor, a drain electrode coupled to a primary voltage supply node and a gate electrode coupled to a secondary voltage supply node, wherein in operation the primary voltage supply node is at a higher voltage than the secondary voltage supply node; and

an output circuit having a pull-up transistor with source and drain electrodes coupled between the primary voltage supply node and a drain electrode of the pull-down transient connectivity limiter transistor, wherein the drain electrode of the pull-up transistor is coupled to the output node and a gate electrode of the pull-up transistor is coupled to a drain electrode of the pull-up transient connectivity limiter transistor, and wherein the output circuit further includes a second pull-up control transistor having source and drain electrodes coupled between the primary voltage supply and the drain electrode of the pull-up transient connectivity limiter transistor and a gate electrode of the second pull-up control transistor is coupled to the drain electrode of the pull-down transient connectivity limiter transistor.

2. The voltage level shifter of claim 1, wherein the transient path connectivity limiter further includes a rapid response pull-up gate control transistor having a source electrode coupled to the gate electrode of the pull-up transient connectivity limiter transistor, a drain electrode coupled to the primary voltage supply node and a gate electrode coupled to the secondary voltage supply node.

3. The voltage level shifter of claim 2, wherein the rapid response pull-down gate control transistor is biased such that in operation when the first node of the input inverter transitions from a low value to a high value, the rapid response pull-down gate control transistor changes from a conducting to a non-conducting state, thereby switching the pull-down transient connectivity limiter transistor from a sub-threshold region of operation to a saturation region of operation.

4. The voltage level shifter of claim 3, wherein the rapid response pull-up gate control transistor is biased such that in operation when the first node of the input inverter transitions from a low value to a high value and the second node of the input inverter transitions from a high value to a low value, the rapid response pull-up gate control transistor changes from a non-conducting state to a conducting state, thereby switching the pull-up transient connectivity limiter transistor from a saturation region of operation to a sub-threshold region of operation.

5. The voltage level shifter of claim 4, wherein the rapid response pull-down gate control transistor is biased such that in operation when the first node of the input inverter transitions from a high value to a low value, the rapid response pull-down gate control transistor changes from a non-conducting to a conducting state, thereby switching the pull-down transient connectivity limiter transistor from a saturation region of operation to a sub-threshold region of operation.

6. The voltage level shifter of claim 5, wherein when the first node of the input inverter transitions from a high value to a low value the second node of the input inverter transitions from a low value to a high value resulting in the rapid response pull-up gate control transistor changing from a conducting state to a non-conducting state, thereby switching the a pull-up transient connectivity limiter transistor from a sub-threshold region of operation to a saturation region of operation.

7. The voltage level shifter of claim 6, wherein the rapid response pull-down gate control transistor and the rapid response pull-up gate control transistor are both native threshold voltage transistors having a substantially zero gate to source threshold voltage.

8. The voltage level shifter of claim 7, wherein the input node is coupled to the input inverter via an initial inverter and the drain electrode of the pull-up transistor is coupled to the output node via an output inverter.

9. The voltage level shifter of claim 7, wherein the input node is coupled to the input inverter via an initial buffer and the drain electrode of the pull-up transistor is coupled to the output node via an output buffer.

10. The voltage level shifter of claim 1, wherein the pull-up transistor is part of a current mirror configuration that includes a mirror transistor coupled between the primary voltage supply and the source of the second pull-up control transistor, and a gate electrode of the mirror transistor is coupled to the gate electrode of the pull-up transistor, and wherein the gate electrode of the pull-up transistor is coupled to the primary voltage supply through a mirror control transistor that has a gate electrode coupled directly to the drain electrode of the pull-up transistor.

11. A voltage level shifter, comprising:

an input node and an output node;

an input circuit with an input inverter coupled to the input node, the input circuit including a pull-down transistor with a gate electrode coupled to a first node of the input inverter and a first pull-up control transistor with a gate electrode coupled to an opposite second node of the input inverter, and wherein source electrodes of the pull-down transistor and the first pull-up control transistor are coupled to a low voltage reference node;

a transient path connectivity limiter including

a pull-down transient connectivity limiter (TCL) transistor having a gate electrode coupled through a first capacitor to the first node of the input inverter and a source electrode coupled to a drain electrode of the pull-down transistor,

a pull-up TCL transistor having a gate electrode coupled through a second capacitor to the second node of the input inverter and a source electrode coupled to a drain electrode of the first pull-up control transistor,

two control inputs coupled to the first and second nodes of the input inverter respectively,

path input nodes coupled to respective drain electrodes of the pull-down transistor and the first pull-up control transistor, and

a rapid response pull-down gate control transistor having a source electrode coupled to the gate electrode of the pull-down TCL transistor, a drain electrode coupled to a primary voltage supply node and a gate electrode coupled to a secondary voltage supply node, wherein in operation the primary voltage supply node is at a higher voltage than the secondary voltage supply node; and

an output circuit having a pull-up transistor with source and drain electrodes coupled between the primary voltage supply node and a pull-down node of the transient path connectivity limiter, wherein the drain electrode of the pull-up transistor is coupled to the output node and a gate electrode of the pull-up transistor is coupled to a pull-up control node of the transient path connectivity limiter, and wherein the output circuit further comprises a second pull-up control transistor having source and drain electrodes coupled between the primary voltage supply and the pull-up control node and a gate electrode of the second pull-up control transistor is coupled to the pull-down node, and wherein during a first transition between voltage levels at the input node the transient path connectivity limiter connects the pull-up control node to the low voltage reference node through the pull-up TCL transistor transitioning from a saturation region of operation to a sub-threshold region of operation, and during the first transition between voltage levels at the input node the transient path connectivity limiter further connects the pull-down control node to the low voltage reference node through the pull-down TCL transistor transitioning from a sub-threshold region of operation to a saturation region of operation.

12. The voltage level shifter of claim 11, wherein during a second opposite transition between voltage levels at the input node the transient path connectivity limiter connects the pull-up control node to the low voltage reference node through the pull-up TCL transistor transitioning from the sub-threshold region of operation to the saturation region of operation and wherein during the second opposite transition between voltage levels at the input node the transient path connectivity limiter further connects the pull-down control node to the low voltage reference node through the pull-down TCL transistor transitioning from the saturation region of operation to the sub-threshold region of operation.

13. The voltage level shifter of claim 11, wherein the transient path connectivity limiter further includes a rapid response pull-up gate control transistor having a source electrode coupled to the gate electrode of the pull-up TCL transistor, a drain electrode coupled to the primary voltage supply node and a gate electrode coupled to the secondary voltage supply node.

14. The voltage level shifter of claim 13, wherein the rapid response pull-down gate control transistor is biased such that in operation when the first node of the input inverter transitions from a low value to a high value, the rapid response pull-down gate control transistor changes from a conducting to a non-conducting state, thereby switching the pull-down TCL transistor from a sub-threshold region of operation to a saturation region of operation.

15. The voltage level shifter of claim 14, wherein the rapid response pull-up gate control transistor is biased such that in operation when the second node of the input inverter is in transition from a low value to a high value, the rapid response pull-up gate control transistor changes from a conducting to a non-conducting state, thereby switching the pull-up TCL transistor from a sub-threshold region of operation to a saturation region of operation.

16. The voltage level shifter of claim 15, wherein the pull-up transistor is part of a current mirror configuration that includes a mirror transistor coupled between the primary voltage supply and the source of the second pull-up control transistor, and a gate electrode of the mirror transistor is coupled to the gate electrode of the pull-up transistor, and wherein the gate electrode of the pull-up transistor is coupled to the primary voltage supply through a mirror control transistor that has a gate electrode coupled directly to the drain electrode of the pull-up transistor.

17. The voltage level shifter of claim 16, wherein, in operation, after the pull-down TCL transistor transitions from the saturation region of operation to the sub-threshold region of operation, the pull-down transistor switches off, and wherein after the pull-up TCL transistor transitions from the saturation region of operation to the sub-threshold region of operation the first pull-up control transistor switches off.