Feed-forward analog-to-digital converter (ADC) with a reduced number of amplifiers and feed-forward signal paths
First Claim
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1. A delta-sigma modulator circuit, comprising:
- a loop filter comprising a plurality of cascaded single op-amp switched-capacitor integrator stages, wherein at least one of the switched-capacitor integrator stages has a switched capacitor input network coupled to an input terminal of the loop filter and to the input of the amplifier and operated according to a clock, a capacitive feedback network connected from an output of an amplifier of the at least one switched-capacitor integrator stage to an input of the amplifier, wherein the capacitive feedback network includes at least two capacitors coupled in series at a common terminal, wherein the common terminal is coupled to a reference voltage source by a switched-capacitor shunt network operated according to the clock; and
a quantizer having an input coupled to the output of the loop filter and an output coupled to an input of the loop filter, wherein the delta-sigma modulator noise-shapes a signal provided to a second input of the loop filter as represented in an average value of the output of the quantizer.
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Abstract
An analog-to-digital converter (ADC) having a reduced number of amplifiers and feed-forward signal paths provides for reduced complexity and power consumption. The analog-to-digital converter includes a delta-sigma modulator having a loop filter with second-order stages implemented with a single amplifier each, provided by a series-connected capacitive feedback network with a switched capacitor shunt. The reduction in the amplifier stages reduces the number of inputs to, and dynamic range required from, the summing node that provides input to the quantizer, as well as reducing the power requirements and complexity of the circuit due to the reduced number of amplifiers.
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Citations
18 Claims
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1. A delta-sigma modulator circuit, comprising:
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a loop filter comprising a plurality of cascaded single op-amp switched-capacitor integrator stages, wherein at least one of the switched-capacitor integrator stages has a switched capacitor input network coupled to an input terminal of the loop filter and to the input of the amplifier and operated according to a clock, a capacitive feedback network connected from an output of an amplifier of the at least one switched-capacitor integrator stage to an input of the amplifier, wherein the capacitive feedback network includes at least two capacitors coupled in series at a common terminal, wherein the common terminal is coupled to a reference voltage source by a switched-capacitor shunt network operated according to the clock; and a quantizer having an input coupled to the output of the loop filter and an output coupled to an input of the loop filter, wherein the delta-sigma modulator noise-shapes a signal provided to a second input of the loop filter as represented in an average value of the output of the quantizer. - View Dependent Claims (2, 3, 4)
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5. An analog-to-digital converter (ADC), comprising:
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a loop filter comprising a plurality of cascaded single op-amp switched-capacitor integrator stages, wherein at least one of the switched-capacitor integrator stages has a switched capacitor input network coupled to an input terminal of the ADC and to the input of the amplifier and operated according to a clock, a capacitive feedback network connected from an output of an amplifier of the at least one switched-capacitor integrator stage to an input of the amplifier, wherein the capacitive feedback network includes at least two capacitors coupled in series at a common terminal, wherein the common terminal is coupled to a reference voltage source by a switched-capacitor shunt network operated according to the clock; a feed-forward network providing feed-forward signals from outputs of at least some of the plurality of cascaded switched-capacitor integrator stages; a summing block for summing the feed-forward signals to generate an output; and a quantizer having an input coupled to the output of the summing block, wherein the feed-forward network provides a predetermined number of feed-forward signals to the summing block. - View Dependent Claims (6, 7, 8, 9, 10)
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11. A switched capacitor integrator stage, comprising:
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an input terminal for receiving an input voltage; an amplifier; a switched capacitor input network coupled to the input terminal and to the input of the amplifier and operated according to a clock; a capacitive feedback network connected from an output of an amplifier of the at least one switched-capacitor integrator stage to an input of the amplifier, wherein the capacitive feedback network includes at least two capacitors coupled in series at a common terminal; and a switched-capacitor shunt network operated according to the clock coupled between the common terminal and a reference voltage source. - View Dependent Claims (12, 13, 14)
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15. A method of operating a delta-sigma modulator, comprising:
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noise-shaping an input and a feedback signal with a loop filter formed by a plurality of cascaded integrator stages, wherein at least one of the plurality of cascaded integrator stages includes a switched capacitor input network coupled to an input terminal of the ADC and to the input of the amplifier and operated according to a clock, a capacitive feedback network connected from an output of an amplifier of the at least one switched-capacitor integrator stage to an input of the amplifier, wherein the capacitive feedback network includes at least two capacitors coupled in series at a common terminal, wherein the common terminal is coupled to a reference voltage source by a switched-capacitor shunt network operated according to the clock; quantizing a result of said noise-shaping to provide an output signal; and providing feedback of said quantizing to said noise-shaping as said feedback signal. - View Dependent Claims (16, 17, 18)
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Specification