Resistor thin film MTP memory

• US 8,644,053 B2
• Filed: 07/29/2013
• Issued: 02/04/2014
• Est. Priority Date: 11/15/2011
• Status: Active Grant

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: Stmicroelectronics Pte Limited (STMicroelectronics NV)
• Inventors: Le Neel, Olivier
• Primary Examiner(s): Nguyen, Viet Q
• Application Number:
  US13/953,626
• Publication Number:
  US 20130314972A1
• Time in Patent Office: 190 Days
• Field of Search: 365/148, 365/189.08, 365/51, 365/63
• US Class Current: 365/148
• CPC Class Codes: G11C 11/21 using electric elements
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0061 Timing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/008 Write by generating heat in the surroundings of the memory material, e.g. thermowrite
• CPC Class Codes: G11C 2213/33 Material including silicon
• CPC Class Codes: G11C 2213/71 Three dimensional array

Abstract

An integrated circuit is formed having an array of memory cells located in the dielectric stack above a semiconductor substrate. Each memory cell has two adjustable resistors and two heating elements. A dielectric material separates the heating elements from the adjustable resistors. One heating element alters the resistance of one of the resistors by applying heat thereto to write data to the memory cell. The other heating element alters the resistance of the other resistor by applying heat thereto to erase data from the memory cell.

Claims

1. A memory device comprising:

a data writing circuit; and

a plurality of memory cells, each memory cell including;

a first thin film adjustable resistor;

a second thin film adjustable resistor;

a first thin film heating element adjacent the first thin film adjustable resistor and coupled to the data writing circuit, the first thin film heating element configured to alter the resistance of the first thin film adjustable resistor by heating the first thin film adjustable resistor;

a second thin film heating element adjacent the second thin film adjustable resistor and coupled to the data writing circuit, the second thin film heating element configured to alter the resistance of the second thin film adjustable resistor by heating the second thin film adjustable resistor; and

a dielectric layer separating the first thin film heating element from the first thin film adjustable resistor and separating the second thin film heating element from the second thin film adjustable resistor.

2. The memory device of claim 1 comprising an integrated circuit die, the memory cells being formed in the integrated circuit die.

3. The memory device of claim 2 comprising transistors in the integrated circuit die.

4. The memory device of claim 1 wherein the first and second thin film adjustable resistors are chromium silicon thin film adjustable resistors.

5. The memory device of claim 1 wherein the first and second thin film heating elements are formed of tantalum.