Packet flow side channel
First Claim
1. A method for embedding a covert side channel communication in an overt communication transmitted over a network using a packet stream comprising:
- a. encoding one or more bits of a side channel communication by;
i. selecting more than one group of related packets from the overt communication being transmitted on a network, each group of packets including a same number of packets, the related packets being consecutive as well as non-consecutive packets; and
ii. relating a packet of one group to a packet of another group to form a pair of packets; and
iii. delaying the timing of at least one packet from each pair of packets;
b. decoding a bit from the side channel communication by;
i. determining inter-packet delays that are the difference in timing between two packets in the pair of packets from the overt communication;
ii. determining at least one inter-packet delay difference between two or more determined inter-packet delays; and
iii. converting the at least one interpacket delay difference into at least one bit.
2 Assignments
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Accused Products
Abstract
A packet flow side channel encoder and decoder embeds and extracts a side channel communication in an overt communication data stream transmitted over a network. The encoder selects more than one group of related packets being transmitted on the network, relates a packet of one group to a packet of another group to form a pair of packets; and delays the timing of at least one packet from each pair of packets The decoder determines inter-packet delays that are the difference in timing between two packets in a pair of packets; determines at least one inter-packet delay difference between two or more determined inter-packet delays; and extracts a bit using the at least one interpacket delay difference.
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Citations
20 Claims
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1. A method for embedding a covert side channel communication in an overt communication transmitted over a network using a packet stream comprising:
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a. encoding one or more bits of a side channel communication by; i. selecting more than one group of related packets from the overt communication being transmitted on a network, each group of packets including a same number of packets, the related packets being consecutive as well as non-consecutive packets; and ii. relating a packet of one group to a packet of another group to form a pair of packets; and iii. delaying the timing of at least one packet from each pair of packets; b. decoding a bit from the side channel communication by; i. determining inter-packet delays that are the difference in timing between two packets in the pair of packets from the overt communication; ii. determining at least one inter-packet delay difference between two or more determined inter-packet delays; and iii. converting the at least one interpacket delay difference into at least one bit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. An apparatus for encoding one or more bits of a covert side channel communication transmitted over a network using a packet stream, comprising:
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a. a packet group selection module configured to select at least two groups of related packets from the overt communication being transmitted on a network, each group of packets including a same number of packets; b. a packet relation module configured to relate a packet of one group to a packet of another group to form a pair of packets; and c. a packet delay module configured to delay the timing of at least one packet from each pair of packets, wherein at least one of the packet group selection module, the packet relation module and the packet delay module is to be implemented by one or more processors of the apparatus. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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17. An apparatus for decoding a bit from a covert side channel communication in an overt communication transmitted over a network using a packet stream, comprising:
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a. an inter-packet delay determination module configured to determine inter-packet delays that are the difference in timing between two packets in a pair of packets from the overt communication; b. a difference determination module configured to determine at least one inter-packet delay difference between two or more determined inter-packet delays; and c. a bit extraction module configured to convert the at least one interpacket delay difference into at least one bit, wherein at least one of the inter-packet delay determination module, the difference determination module and the bit extraction module is to be implemented by one or more processors of the apparatus. - View Dependent Claims (18, 19, 20)
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Specification