Method and apparatus for performing model-based OPC for pattern decomposed features

• US 8,644,589 B2
• Filed: 03/05/2013
• Issued: 02/04/2014
• Est. Priority Date: 09/13/2006
• Status: Expired due to Fees

• Current Assignee: ASML Netherlands BV (ASML Holding NV)
• Original Assignee: ASML Masktools B.V. (ASML Holding NV)
• Inventors: Hsu, Duan-Fu Stephen, Van Den Broeke, Doug, Chen, Jang Fung, Park, Jungchul
• Primary Examiner(s): Tabatabai, Abolfazl
• Application Number:
  US13/786,249
• Publication Number:
  US 20130182940A1
• Time in Patent Office: 336 Days
• Field of Search: 382/159, 382/165, 382/170, 382/181, 382/194, 382/309, 703/14, 715/52, 716/52, 716/53, 716/55, 716/106, 725/19
• US Class Current: 382/144
• CPC Class Codes: G03F 1/36 Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
• CPC Class Codes: G03F 1/70 Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
• CPC Class Codes: G03F 7/70466 Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature stitching G03F7/70475
• CPC Class Codes: G03F 7/70475 Stitching, i.e. connecting image fields to produce a device field, the field occupied by a device such as a memory chip, processor chip, CCD, flat panel display
• CPC Class Codes: G06T 7/0004 Industrial image inspection

Abstract

A method for decomposing a target circuit pattern containing features to be imaged into multiple patterns. The process includes the steps of separating the features to be printed into a first pattern and a second pattern; performing a first optical proximity correction process on the first pattern and the second pattern; determining an imaging performance of the first pattern and the second pattern; determining a first error between the first pattern and the imaging performance of the first pattern, and a second error between the second pattern and the imaging performance of said second pattern; utilizing the first error to adjust the first pattern to generate a modified first pattern; utilizing the second error to adjust the second pattern to generate a modified second pattern; and applying a second optical proximity correction process to the modified first pattern and the modified second pattern.

Claims

1. A computer-implemented method of performing optical proximity correction (OPC) of target circuit patterns that are decomposed into multiple sub-patterns, the multiple sub-patterns being configured to be imaged using a multiple patterning lithography process, the method comprising:

applying OPC parameters to each sub-pattern;

using feature geometries of the target circuit patterns and Boolean operations to extract overlap areas for each sub-pattern;

determining printing contour errors in the overlap areas with respect to intended target circuit patterns;

using Boolean operations to convert the determined printing contour errors into polygons that are added to the overlap areas, thereby generating modified sub-patterns; and

combining the modified sub-patterns to obtain an improved layout of the target circuit patterns.

2. The method of claim 1, wherein prior to combining the modified sub-patterns, applying a further round of OPC parameters to the modified sub-patterns.

3. The method of claim 2, wherein the method further comprises:

verifying that the improved layout of the target circuit pattern produces an improved printing contour when imaged using a simulated model of the multiple patterning lithography process.

4. The method of claim 3, wherein the step of verifying comprises verifying that an average intensity modulation in the overlap areas is substantially flat.

5. The method of claim 1, wherein one or more steps of the method are repeated until the improved printing contour matches a desired printing contour.

6. The method of claim 5, wherein the OPC parameters and the further round of OPC parameters are dynamically updated.

7. The method of claim 1, wherein initial OPC parameters comprise reference OPC parameters associated with a baseline imaging performance.

8. The method of claim 7, wherein the OPC parameters include scatter bars as assist patterns that improve imaging performance.

9. The method of claim 1, wherein the target circuit patterns are decomposed using a coloring line (CLN) method.

10. The method of claim 1, wherein the target circuit patterns are decomposed using a coloring space (CSP) method.

11. The method of claim 1, wherein the target circuit patterns represent a full chip layout or a portion thereof.

12. A non-transitory computer-readable storage medium storing a computer program having computer-executable instructions for causing a computer to perform the steps of the method in claim 1.