Clock simulation device and methods thereof

• US 8,645,117 B2
• Filed: 05/27/2010
• Issued: 02/04/2014
• Est. Priority Date: 05/27/2010
• Status: Expired due to Fees

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Yin, Qichao R., Yen, Jen-Tien, Wong, Wai Chee
• Primary Examiner(s): Fernandez Rivas, Omar
• Assistant Examiner(s): GEBRESILASSIE, KIBROM K
• Application Number:
  US12/788,769
• Publication Number:
  US 20110295586A1
• Time in Patent Office: 1,349 Days
• Field of Search: 703/13, 703/14, 703/19, 713/400, 713/500, 713/600, 716/108, 716/113, 708/271
• US Class Current: 703/19
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A pulse width of a simulated external system clock is set by determining a least common multiple of the frequency of selected internal clock signals relative to the frequency of the external system clock. The pulse width can be further adjusted based on the frequency of simulated external clocks. By setting the pulse width of the simulated external system clock based on the least common multiple value, the time required to complete the simulation can be reduced while ensuring proper operation of the simulated clock signals during the simulation.

Claims

1. A method comprising:

receiving a design file representative of a data processing device;

receiving at a computer a first frequency value indicating a frequency of a first external clock signal to be provided to a first external interface of the data processing device;

receiving at the computer a second frequency value indicating a frequency of a second external clock signal to be provided to a second external interface of the data processing device;

identifying a plurality of internal clock signals corresponding to internal nodes of the data processing device, the internal clock signals generated internally by one or more modules of the data processing device;

for each internal clock signal of the plurality of internal clock signals, determining a multiplier expressing a ratio between a frequency of the internal clock signal and the first frequency value, thereby determining a plurality of multipliers;

determining at the computer a first least common multiple representing a least common multiple of the plurality of multipliers;

determining at the computer a second least common multiple representing a least common multiple of the first frequency value and the second frequency value;

determining at the computer a first pulse width of the first external clock signal based on the first least common multiple and the second least common multiple; and

simulating operation of the data processing device based on the first external clock signal having the first pulse width.

2. The method of claim 1, further comprising:

determining a subset of the plurality of internal clock signals based on configuration information, the subset excluding at least one of the plurality of internal clock signals; and

wherein determining the first least common multiple comprises determining the first least common multiple based only on a subset of the plurality of multipliers associated with the subset of the plurality of internal clock signals.

3. The method of claim 2, wherein determining the subset of the plurality of internal clock signals comprises:

determining, based on the configuration information, that a first clock domain of the data processing device is not to be simulated; and

excluding a clock signal associated with the first clock domain from the subset of the plurality of internal clock signals.

4. The method of claim 1, further comprising:

in response to determining, based on configuration information, that a first clock domain of the data processing device is to be simulated in a first mode of operation;

adjusting a first frequency value of a first clock of the plurality of internal clock signals by a first factor to determine an adjusted frequency value; and

determining the first least common multiple based on the first adjusted frequency value.

5. The method of claim 4, further comprising:

in response to determining that the first clock domain is to be simulated in a second mode of operation, determining the first least common multiple based on the first frequency value without adjusting the first frequency value by the first factor.

6. The method of claim 5, wherein the first mode of operation comprises a synchronous mode of operation and the second mode of operation comprises an asynchronous mode of operation.

7. The method of claim 1, further comprising:

determining, based on configuration information, that a first clock generation module of the data processing device is associated with a clock adjustment factor;

adjusting a first frequency value of a first clock of the plurality of internal clocks by the clock adjustment factor to determine an adjusted frequency value; and

determining the first least common multiple based on the adjusted frequency value.

8. The method of claim 1, further comprising:

determining a pulse width of the second external clock signal based on the first least common multiple and the second least common multiple.

9. The method of claim 1, further comprising:

adjusting the design file of the data processing device based on simulating operation of the data processing device; and

forming an integrated circuit based on the design file.

10. A method, comprising:

receiving a design file representative of a data processing device;

determining at a computer a plurality of external clock signals to be simulated, each external clock signal of the plurality of external clock signals to be provided to corresponding external interfaces of the data processing device, the plurality of external clock signals including a first external clock signal having a first frequency;

determining at the computer a plurality of internal clock signals of the data processing device, the internal clock signals corresponding to internal nodes of the data processing device, the internal clock signals generated internally by one or more modules of the data processing device;

for each internal clock signal of the plurality of internal clock signals, determining a ratio between a frequency of the internal clock signal and the first frequency, thereby determining a plurality of frequency ratios;

determining at the computer a first least common multiple representing a least common multiple of the plurality of frequency ratios;

determining at the computer a second least common multiple representing a least common multiple of a frequency of each of the plurality of external clock signals;

setting a number of simulation time intervals associated with the first external clock signal to be simulated based on the first least common multiple and the second least common multiple; and

simulating, at the computer operation of the data processing device based on the first external clock signal by determining a simulated state of the data processing device at each of the simulation time intervals.

11. The method of claim 10, further comprising:

in response to determining that a first clock domain of the data processing device is to be simulated, including a first internal clock signal associated with the first clock domain in the plurality of internal clock signals; and

in response to determining a second clock domain available of the data processing device is not to be simulated, excluding a second internal clock signal associated with the second clock domain from the plurality of internal clock signals.

12. A non-transitory computer readable medium storing a set of instructions, the set of instructions comprising instructions to manipulate a processing system to:

determine a first least common multiple representing a least common multiple of a first plurality of frequency values, each of the first plurality of frequency values indicating a frequency of a corresponding one of a plurality of external clock signals available to be simulated, each external clock signal of the plurality of external clock signals to be provided to a corresponding external interface of a data processing device to be simulated, the plurality of external clock signals including a first external clock signal having a first frequency;

determine a second least common multiple representing a least common multiple of plurality of a frequency ration, each frequency ratio of the plurality of frequency ratios expressing a ratio between a frequency of an internal clock signal of a plurality of internal clock signals and the first frequency, the internal clock signals corresponding to internal nodes of the data processing device, the internal clock signals generated internally by of one or more modules of the data processing device;

determine a first pulse width of a first clock signal of the plurality of clock signals based on the first least common multiple and the second least common multiple; and

simulate operation of the data processing device based on the first external clock signal having the first pulse width.

13. The computer readable medium of claim 12, wherein the set of instructions further comprises instructions to:

determine a subset of the plurality of internal clock signals based on configuration information, the subset excluding at least one of the plurality of internal clock signals; and

wherein determining the second least common multiple comprises determining the second least common multiple based on a subset of the plurality of frequency ratios associated with the subset of the plurality of internal clock signals.

14. The computer readable medium of claim 13, wherein the instructions to determine the subset of the plurality of clock signals comprise instructions to:

determine, based on the configuration information, that a first clock domain of the data processing device is not to be simulated; and

exclude a clock signal associated with the first clock domain from the subset of the plurality of internal clock signals.

15. The computer readable medium of claim 13, wherein the set of instructions further comprises instructions to:

in response to determining, based on configuration information, that a first clock domain of the data processing device is to be simulated operating in a first mode;

adjust a first frequency value of a first clock of the plurality of internal clock signals by a first factor to determine an adjusted frequency value; and

determine the second least common multiple based on the first adjusted frequency value.

16. The computer readable medium of claim 15, wherein the set of instructions further comprises instructions to:

in response to determining that the first clock domain is to be simulated operating in a second mode, determine the second least common multiple based on the first frequency value without adjusting the first frequency value of the first clock of the plurality of internal clock signals by the first factor.

17. The computer readable medium of claim 16, wherein the first mode comprises a synchronous mode of operation and the second mode comprises an asynchronous mode of operation.

18. The computer readable medium of claim 13, wherein the set of instructions further comprises instructions to:

in response to determining, based on configuration information, that a first clock generation module of the data processing device is associated with a clock adjustment factor;

adjust a first frequency value of a first clock of the plurality of internal clocks by the clock adjustment factor to determine an adjusted frequency value; and

determine the second least common multiple based on the first adjusted frequency value.