Combined floating point adder and subtractor

• US 8,645,449 B1
• Filed: 03/03/2009
• Issued: 02/04/2014
• Est. Priority Date: 03/03/2009
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Langhammer, Martin
• Primary Examiner(s): Alrobaye, Idriss N
• Assistant Examiner(s): Lewis-Taylor, Dayton
• Application Number:
  US12/396,826
• Time in Patent Office: 1,799 Days
• Field of Search: None
• US Class Current: 708/505
• CPC Class Codes: G06F 7/485 Adding; Subtracting G06F7/4833, G06F7/4836 take precedence

Abstract

Circuitry (fixed or configured in a programmable device) for performing floating point addition and subtraction uses approximately the same resources as required for either operation separately. The circuitry is based on a recognition that when adding or subtracting two numbers, the two resulting mantissa values will be two out of three possibilities, and will involve either a one-bit shifting operation, or a shifting operation involving a large number of bits. Therefore, one mantissa path—a subtraction path—can be provided with full add/normalize/round circuitry, while a second mantissa path—an addition path—can be provided with a simple one-bit shifter and simplified rounding circuitry. Because the input numbers are signed, the “addition path,” which only adds the mantissas, may provide the mantissa for the subtraction result, depending on the signs of the input numbers. Similarly, the “subtraction path” may provide the mantissa for the addition result.

Claims

1. Combined floating-point addition and subtraction circuitry for both adding and subtracting a first signed floating-point input number and a second signed floating-point input number, wherein each of said first and second signed floating-point input numbers has a respective sign, a respective mantissa and a respective exponent, to provide a sum and a difference of said first and second signed floating-point numbers, said combined floating-point addition and subtraction circuitry comprising:

a first mantissa computation path including a first adder for adding said mantissas of said first and second signed floating-point numbers, a one-bit right-shifting circuit for controllably shifting output of said first adder to normalize said output of said first adder, and rounding circuitry for (a) providing a first candidate mantissa and (b) providing a first exponent-adjustment bit;

a second mantissa computation path including a first subtractor for subtracting said mantissa of said second signed floating-point number from said mantissa of said first signed floating-point number to provide a first mantissa difference, a second subtractor for subtracting said mantissa of said first signed floating-point number from said mantissa of said second signed floating-point number to provide a second mantissa difference, a selector for selecting as a mantissa difference output one of said first and second mantissa differences that is positive, and a normalize-and-round circuit for (a) providing a second candidate mantissa and (b) providing a second exponent-adjustment bit; and

a selection stage that selects, based on said respective signs, both (a) a mantissa of said sum of said first and second signed floating point numbers from among inputs including both of said first and second candidate mantissas, and (b) a mantissa of said difference of said first and second signed floating point numbers from among inputs including both of said first and second candidate mantissas.

2. The combined floating-point addition and subtraction circuitry of claim 1 further comprising a shared input stage that determines a larger and a smaller one of said respective exponents, determines a difference between said larger exponent and said smaller exponent, and right-shifts, by said difference between said larger exponent and said smaller exponent, said respective mantissa of said one of said input floating-point numbers having said smaller exponent.

3. The combined floating-point addition and subtraction circuitry of claim 1 wherein:

said first and second mantissa differences are represented by a number format in which one bit represents sign;

said selector is a multiplexer; and

said one bit of one of said mantissa differences is used as a control bit for said multiplexer.

4. The combined floating-point addition and subtraction circuitry of claim 1 wherein:

said selection stage comprises a plurality of selection stage multiplexers; and

said respective signs determine control bits for said selection stage multiplexers.

5. The combined floating-point addition and subtraction circuitry of claim 4 wherein:

said selection stage comprises two mantissa selection multiplexers for selecting said one of said first and second candidate mantissas;

one of said mantissa selection multiplexers receives said first candidate mantissa at a first input thereof and said second candidate mantissa at a second input thereof;

another of said mantissa selection multiplexers receives said second candidate mantissa at a first input thereof and said first candidate mantissa at a second input thereof; and

said control bits select one of (a) both said first inputs, and (b) both said second inputs.

6. The combined floating-point addition and subtraction circuitry of claim 1 further comprising:

a shared input stage that determines a larger and a smaller one of said respective exponents and selects said larger exponent as an input stage output exponent;

a first exponent computation path for combining said input stage output exponent and said first exponent adjustment bit to provide a first candidate exponent; and

a second exponent computation path for combining said input stage output exponent and said second exponent adjustment bit to provide a second candidate exponent;

wherein;

said selection stage also selects one of said first and second candidate exponents for said sum of said first and second signed floating point numbers, and another one of said first and second candidate exponents for said difference of said first and second signed floating point numbers.

7. The combined floating-point addition and subtraction circuitry of claim 6 wherein:

said selection stage comprises two exponent selection multiplexers for selecting said one of said first and second candidate exponents;

one of said exponent selection multiplexers receives said first candidate exponent at a first input thereof and said second candidate exponent at a second input thereof;

another of said exponent selection multiplexers receives said second candidate exponent at a first input thereof and said first candidate exponent at a second input thereof; and

said control bits select one of (a) both said first inputs, and (b) both said second inputs.

8. The combined floating-point addition and subtraction circuitry of claim 1 further comprising a sign assignment stage for assigning a respective sign to said sum of said first and second signed floating point numbers and to said difference of said first and second signed floating point numbers.

9. A method of configuring a programmable integrated circuit device as combined floating-point addition and subtraction circuitry for both adding and subtracting a first signed floating-point input number and a second signed floating-point input number, wherein each of said first and second signed floating-point input numbers has a respective sign, a respective mantissa and a respective exponent, to provide a sum and a difference of said first and second signed floating-point numbers, said method comprising:

configuring logic of said programmable integrated circuit device as a first mantissa computation path including a first adder for adding said mantissas of said first and second signed floating-point numbers, a one-bit right-shifting circuit for controllably shifting output of said first adder to normalize said output of said first adder, and rounding circuitry for (a) providing a first candidate mantissa and (b) providing a first exponent-adjustment bit;

configuring logic of said programmable integrated circuit device as a second mantissa computation path including a first subtractor for subtracting said mantissa of said second signed floating-point number from said mantissa of said first signed floating-point number to provide a first mantissa difference, a second subtractor for subtracting said mantissa of said first signed floating-point number from said mantissa of said second signed floating-point number to provide a second mantissa difference, a selector for selecting as a mantissa difference output one of said first and second mantissa differences that is positive, and a normalize-and-round circuit for (a) providing a second candidate mantissa and (b) providing a second exponent-adjustment bit; and

configuring logic of said programmable integrated circuit device as a selection stage for selecting, based on said respective signs, both (a) a mantissa of said sum of said first and second signed floating point numbers from among inputs including both of said first and second candidate mantissas, and (b) a mantissa of said difference of said first and second signed floating point numbers from among inputs including both of said first and second candidate mantissas.

10. The method of claim 9 further comprising configuring logic of said programmable integrated circuit device as a shared input stage that determines a larger and a smaller one of said respective exponents, determines a difference between said larger exponent and said smaller exponent, and right-shifts, by said difference between said larger exponent and said smaller exponent, said respective mantissa of said one of said input floating-point numbers having said smaller exponent.

11. The method of claim 9 wherein:

said first and second mantissa differences are represented by a number format in which one bit represents sign; and

said configuring logic of said programmable integrated circuit device as a second mantissa computation path comprises;

configuring a multiplexer as said selector, and

configuring said one bit of one of said mantissa differences to be used as a control bit for said multiplexer.

12. The method of claim 9 wherein said configuring logic of said programmable integrated circuit device as a selection stage comprises:

configuring logic of said programmable integrated circuit device as a plurality of selection stage multiplexers; and

configuring said respective signs to determine control bits for said selection stage multiplexers.

13. The method of claim 12 wherein said configuring logic of said programmable integrated circuit device as a selection stage further comprises:

configuring logic of said programmable integrated circuit device as two mantissa selection multiplexers for selecting said one of said first and second candidate mantissas;

configuring one of said mantissa selection multiplexers to receive said first candidate mantissa at a first input thereof and said second candidate mantissa at a second input thereof;

configuring another of said mantissa selection multiplexers to receive said second candidate mantissa at a first input thereof and said first candidate mantissa at a second input thereof; and

configuring said control bits to select one of (a) both said first inputs, and (b) both said second inputs.

14. The method of claim 9 further comprising:

configuring logic of said programmable integrated circuit device as a shared input stage that determines a larger and a smaller one of said respective exponents and selects said larger exponent as an input stage output exponent;

configuring logic of said programmable integrated circuit device as a first exponent computation path for combining said input stage output exponent and said first exponent adjustment bit to provide a first candidate exponent; and

configuring logic of said programmable integrated circuit device as a second exponent computation path for combining said input stage output exponent and said second exponent adjustment bit to provide a second candidate exponent;

wherein;

configuring logic of said programmable integrated circuit device as a selection stage comprises also configuring said selection stage to select one of said first and second candidate exponents for said sum of said first and second signed floating point numbers, and another one of said first and second candidate exponents for said difference of said first and second signed floating point numbers.

15. The method of claim 14 wherein said configuring logic of said programmable integrated circuit device as a selection stage further comprises:

configuring logic of said programmable integrated circuit device as two exponent selection multiplexers for selecting said one of said first and second candidate exponents;

configuring one of said exponent selection multiplexers to receive said first candidate exponent at a first input thereof and said second candidate exponent at a second input thereof;

configuring another of said exponent selection multiplexers to receive said second candidate exponent at a first input thereof and said first candidate exponent at a second input thereof; and

configuring said control bits to select one of (a) both said first inputs, and (b) both said second inputs.

16. The method of claim 9 further comprising configuring logic of said programmable integrated circuit device as a sign assignment stage for assigning a respective sign to said sum of said first and second signed floating point numbers and to said difference of said first and second signed floating point numbers.

17. A programmable integrated circuit device configured as combined floating-point addition and subtraction circuitry for both adding and subtracting a first signed floating-point input number and a second signed floating-point input number, wherein each of said first and second signed floating-point input numbers has a respective sign, a respective mantissa and a respective exponent, to provide a sum and a difference of said first and second signed floating-point numbers, said configured programmable integrated circuit device comprising:

logic configured as a first mantissa computation path including a first adder for adding said mantissas of said first and second signed floating-point numbers, a one-bit right-shifting circuit for controllably shifting output of said first adder to normalize said output of said first adder, and rounding circuitry for (a) providing a first candidate mantissa and (b) providing a first exponent-adjustment bit;

logic configured as a second mantissa computation path including a first subtractor for subtracting said mantissa of said second signed floating-point number from said mantissa of said first signed floating-point number to provide a first mantissa difference, a second subtractor for subtracting said mantissa of said first signed floating-point number from said mantissa of said second signed floating-point number to provide a second mantissa difference, a selector for selecting as a mantissa difference output one of said first and second mantissa differences that is positive, and a normalize-and-round circuit for (a) providing a second candidate mantissa and (b) providing a second exponent-adjustment bit; and

logic configured as a selection stage for selecting, based on said respective signs, both (a) a mantissa of said sum of said first and second signed floating point numbers from among inputs including both of said first and second candidate mantissas, and (b) a mantissa of said difference of said first and second signed floating point numbers from among inputs including both of said first and second candidate mantissas.

18. The configured programmable integrated circuit device of claim 17 further comprising logic configured as a shared input stage that determines a larger and a smaller one of said respective exponents, determines a difference between said larger exponent and said smaller exponent, and right-shifts, by said difference between said larger exponent and said smaller exponent, said respective mantissa of said one of said input floating-point numbers having said smaller exponent.

19. The configured programmable integrated circuit device of claim 17 wherein:

said first and second mantissa differences are represented by a number format in which one bit represents sign;

a multiplexer is configured as said selector; and

said one bit of one of said mantissa differences is configured to be used as a control bit for said multiplexer.

20. The configured programmable integrated circuit device of claim 17 wherein said logic configurable as a selection stage comprises:

logic configured as a plurality of selection stage multiplexers; and

logic configured to determine control bits for said selection stage multiplexers from said respective signs.

21. The configured programmable integrated circuit device of claim 20 wherein:

said logic configured as a selection stage further comprises logic configured as two mantissa selection multiplexers for selecting said one of said first and second candidate mantissas;

logic configured as one of said mantissa selection multiplexers is configured to receive said first candidate mantissa at a first input thereof and said second candidate mantissa at a second input thereof; and

logic configured as another of said mantissa selection multiplexers is configured to receive said second candidate mantissa at a first input thereof and said first candidate mantissa at a second input thereof;

said logic configured as a selection stage further comprising;

logic configured to use said control bits to select one of (a) both said first inputs, and (b) both said second inputs.

22. The configured programmable integrated circuit device of claim 17 further comprising:

logic configured as a shared input stage that determines a larger and a smaller one of said respective exponents and selects said larger exponent as an input stage output exponent;

logic configured as a first exponent computation path for combining said input stage output exponent and said first exponent adjustment bit to provide a first candidate exponent; and

logic configured as a second exponent computation path for combining said input stage output exponent and said second exponent adjustment bit to provide a second candidate exponent;

wherein;

said logic configured as said selection stage is also configured to select one of said first and second candidate exponents for said sum of said first and second signed floating point numbers, and another one of said first and second candidate exponents for said difference of said first and second signed floating point numbers.

23. The configured programmable integrated circuit device of claim 22 wherein:

said logic configured as a selection stage further comprises logic configured as two exponent selection multiplexers for selecting said one of said first and second candidate exponents;

said logic configured as one of said exponent selection multiplexers is configured to receive said first candidate exponent at a first input thereof and said second candidate exponent at a second input thereof; and

said logic configured as another of said exponent selection multiplexers is configurable to receive said second candidate exponent at a first input thereof and said first candidate exponent at a second input thereof;

said logic configured as a selection stage further comprising;

logic configured to use said control bits to select one of (a) both said first inputs, and (b) both said second inputs.

24. The configured programmable integrated circuit device of claim 17 further comprising logic configured as a sign assignment stage for assigning a respective sign to said sum of said first and second signed floating point numbers and to said difference of said first and second signed floating point numbers.

25. A non-transitory machine-readable data storage medium encoded with machine-executable instructions for configuring a programmable integrated circuit device as combined floating-point addition and subtraction circuitry for both adding and subtracting a first signed floating-point input number and a second signed floating-point input number, wherein each of said first and second signed floating-point input numbers has a respective sign, a respective mantissa and a respective exponent, to provide a sum and a difference of said first and second signed floating-point numbers, said instructions comprising:

instructions to configure logic of said programmable integrated circuit device as a first mantissa computation path including a first adder for adding said mantissas of said first and second signed floating-point numbers, a one-bit right-shifting circuit for controllably shifting output of said first adder to normalize said output of said first adder, and rounding circuitry for (a) providing a first candidate mantissa and (b) providing a first exponent-adjustment bit;

instructions to configure logic of said programmable integrated circuit device as a second mantissa computation path including a first subtractor for subtracting said mantissa of said second signed floating-point number from said mantissa of said first signed floating-point number to provide a first mantissa difference, a second subtractor for subtracting said mantissa of said first signed floating-point number from said mantissa of said second signed floating-point number to provide a second mantissa difference, a selector for selecting as a mantissa difference output one of said first and second mantissa differences that is positive, and a normalize-and-round circuit for (a) providing a second candidate mantissa and (b) providing a second exponent-adjustment bit; and

instructions to configure logic of said programmable integrated circuit device as a selection stage for selecting, based on said respective signs, both (a) a mantissa of said sum of said first and second signed floating point numbers from among inputs including both of said first and second candidate mantissas, and (b) a mantissa of said difference of said first and second signed floating point numbers from among inputs including both of said first and second candidate mantissas.

26. The non-transitory machine-readable data storage medium of claim 25 wherein said instructions further comprise:

instructions to configure logic of said programmable integrated circuit device as a shared input stage that determines a larger and a smaller one of said respective exponents, determines a difference between said larger exponent and said smaller exponent, and right-shifts, by said difference between said larger exponent and said smaller exponent, said respective mantissa of said one of said input floating-point numbers having said smaller exponent.

27. The non-transitory machine-readable data storage medium of claim 25 wherein said instructions to configure logic of said programmable integrated circuit device as a selection stage comprise:

instructions to configure logic of said programmable integrated circuit device as a plurality of selection stage multiplexers; and

instructions to configure said respective signs to determine control bits for said selection stage multiplexers.

28. The non-transitory machine-readable data storage medium of claim 27 wherein said instructions further comprise:

instructions to configure logic of said programmable integrated circuit device as a shared input stage that determines a larger and a smaller one of said respective exponents and selects said larger exponent as an input stage output exponent;

instructions to configure logic of said programmable integrated circuit device as a first exponent computation path for combining said input stage output exponent and said first exponent adjustment bit to provide a first candidate exponent; and

instructions to configure logic of said programmable integrated circuit device as a second exponent computation path for combining said input stage output exponent and said second exponent adjustment bit to provide a second candidate exponent;

wherein;

said instructions to configure logic of said programmable integrated circuit device as a selection stage also comprise instructions to configure said selection stage to select one of said first and second candidate exponents for said sum of said first and second signed floating point numbers, and another one of said first and second candidate exponents for said difference of said first and second signed floating point numbers.