Double-clocked specialized processing block in an integrated circuit device

• US 8,645,451 B2
• Filed: 03/10/2011
• Issued: 02/04/2014
• Est. Priority Date: 03/10/2011
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Langhammer, Martin
• Primary Examiner(s): Malzahn, David H
• Application Number:
  US13/044,680
• Publication Number:
  US 20120233230A1
• Time in Patent Office: 1,062 Days
• Field of Search: None
• US Class Current: 708/620
• CPC Class Codes: G06F 7/5324 partitioned, i.e. using repetitively a smaller parallel parallel multiplier or using an array of such smaller multipliers

Abstract

Circuitry for increasing the precision of multipliers by a desired factor while limiting the increase in arithmetic complexity of the multiplier to that factor can be provided in a fixed logic device, or can be configured into a programmable integrated circuit device such as a programmable logic device (PLD). The smaller increase in arithmetic complexity, so that the increase is proportional to the increase in precision, rather than to the square of the increase in precision, is achieved by using specialized processing block components differently on alternating clock cycles. For example, to implement double precision, the same multiplier components are used in each of two clock cycles, but some specialized processing block internal structures (e.g., shifters and adders) are used differently in the two cycles, so that over the two cycles, a larger multiplication may be calculated from smaller partial products.

Claims

1. A block of circuitry, within an integrated circuit device clocked by a device clock signal, said block of circuitry being clocked by a block clock signal and comprising:

block inputs for accepting data, input from outside said block of circuitry, on which arithmetic operations are to be performed;

arithmetic operations circuitry having arithmetic inputs coupled to said block inputs, for performing said arithmetic operations on said data; and

logical operations circuitry for operating on outputs of said arithmetic operations circuitry;

wherein;

said arithmetic operations circuitry is configured to operate substantially identically on substantially all clock pulses of said block clock signal; and

said logic operations circuitry is configured to operate in a first mode on a first set of clock pulses of said block clock signal, and to operate in a second mode on a second set of clock pulses of said block clock signal interleaved with said first set of clock pulses.

2. The block of circuitry of claim 1 wherein said block clock signal is identical to said device clock signal.

3. The block of circuitry of claim 2 wherein said block of circuitry operates on both rising and falling edges of said block clock signal.

4. The block of circuitry of claim 1 wherein said block clock signal is faster than said device clock signal.

5. The block of circuitry of claim 4 wherein said block clock signal is an integer multiple of said device clock signal.

6. The block of circuitry of claim 1 wherein said logic operations circuitry comprises at least one shifter and at least one accumulator.

7. The block of circuitry of claim 6 wherein said at least one shifter comprises a shifter that is operable to shift a first amount in said first mode and a second amount in said second mode.

8. The block of circuitry of claim 7 wherein one of said first amount and said second amount is no shifting.

9. The block of circuitry of claim 7 wherein said first and second amounts are in the same direction but of different magnitudes.

10. The block of circuitry of claim 7 wherein said first and second amounts are in different directions.

11. The block of circuitry of claim 1 further comprising input circuitry configured to operate differently during said second mode than during said first mode.

12. The block of circuitry of claim 11 wherein said input circuitry comprises multiplexers.

13. A programmable integrated circuit device comprising at least one block of circuitry as in claim 1.

14. A method of configuring a programmable integrated circuit device, having at least one specialized processing block, each said specialized processing block being clocked by a respective block clock signal and said integrated circuit device being clocked by a device clock signal, each said specialized processing block having block inputs for accepting data, on which arithmetic operations are to be performed, input from outside said at least one specialized processing block, arithmetic operations circuitry having arithmetic inputs connected to said block inputs for performing said arithmetic operations on said data, and logical operations circuitry for operating on outputs of said arithmetic operations circuitry, said method comprising:

configuring said arithmetic operations circuitry of at least one of said at least one specialized processing block to operate substantially identically on substantially all clock pulses of said respective block clock signal; and

configuring said logic operations circuitry of each at least one of said at least one specialized processing block to operate in a first mode on a first set of clock pulses of said respective block clock signal, and to operate in a second mode on a second set of clock pulses of said respective block clock signal interleaved with said first set of clock pulses.

15. The method of claim 14 further comprising configuring each said respective block clock signal to be identical to said device clock signal.

16. The method of claim 15 further comprising configuring said specialized processing block to operate on both rising and falling edges of said block clock signal.

17. The method of claim 14 further comprising configuring each said respective block clock signal to be faster than said device clock signal.

18. The method of claim 17 further comprising configuring each said respective block clock signal to be an integer multiple of said device clock signal.

19. The method of claim 14 further comprising configuring said logic operations circuitry of at least one of said at least one specialized processing block as at least one shifter and at least one accumulator.

20. The method of claim 19 further comprising configuring said at least one shifter to shift a first amount in said first mode and a second amount in said second mode.

21. The method of claim 20 wherein one of said first amount and said second amount is no shifting.

22. The method of claim 20 wherein said first and second amounts are in the same direction but of different magnitudes.

23. The method of claim 20 wherein said first and second amounts are in different directions.

24. A non-transitory machine-readable data storage medium encoded with non-transitory machine-executable instructions for configuring a programmable integrated circuit device, having at least one specialized processing block, each of said at least one specialized processing block being clocked by a respective block clock signal and said integrated circuit device being clocked by a device clock signal, each of said at least one specialized processing block having block inputs for accepting data, input from outside said at least one specialized processing block, on which arithmetic operations are to be performed, arithmetic operations circuitry having arithmetic inputs connected to said block inputs for performing arithmetic operations on said data, and logical operations circuitry operating on outputs of said arithmetic operations circuitry, said instructions comprising:

instructions to configure said arithmetic operations circuitry of at least one of said at least one specialized processing block to operate substantially identically on substantially all clock pulses of said block clock signal; and

instructions to configure said logic operations circuitry of at least one of said at least one specialized processing block to operate in a first mode on a first set of clock pulses of said block clock signal, and to operate in a second mode on a second set of clock pulses of said block clock signal interleaved with said first set of clock pulses.

25. The machine-readable data storage medium of claim 24 further comprising instructions to configure said respective block clock signal to be identical to said device clock signal.

26. The machine-readable data storage medium of claim 25 further comprising instructions to configure said block to operate on both rising and falling edges of said block clock signal.

27. The machine-readable data storage medium of claim 24 further comprising instructions to configure said respective block clock signal to be faster than said device clock signal.

28. The machine-readable data storage medium of claim 27 wherein said instructions to configure said respective block clock signal to be faster than said device clock signal comprise instructions to configure said respective block clock signal to be an integer multiple of said device clock signal.

29. The machine-readable data storage medium of claim 24 further comprising instructions to configure said logic operations circuitry of at least one of said at least specialized processing block as at least one shifter and at least one accumulator.

30. The machine-readable data storage medium of claim 29 further comprising instructions to configure said at least one shifter to shift a first amount in said first mode and a second amount in said second mode.

31. The machine-readable data storage medium of claim 30 wherein, in said instructions to configure said at least one shifter, one of said first amount and said second amount is no shifting.

32. The machine-readable data storage medium of claim 30 wherein, in said instructions to configure said at least one shifter, said first and second amounts are in the same direction but of different magnitudes.

33. The machine-readable data storage medium of claim 30 wherein, in said instructions to configure said at least one shifter, said first and second amounts are in different directions.