Circuit and electronic module for automatic addressing

• US 8,645,580 B2
• Filed: 09/06/2011
• Issued: 02/04/2014
• Est. Priority Date: 09/06/2011
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Koudar, Ivan
• Primary Examiner(s): Alrobaye, Idriss N
• Assistant Examiner(s): Franklin, Richard B
• Application Number:
  US13/226,025
• Publication Number:
  US 20130057339A1
• Time in Patent Office: 882 Days
• Field of Search: None
• US Class Current: 710/3
• CPC Class Codes: G06F 13/4252 using a handshaking protocol
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An integrated circuit includes a first configuration terminal, a second configuration terminal, a bus terminal, and an auto addressing circuit coupled to the first and second configuration terminals. The auto addressing circuit is responsive to a data pattern received at the first configuration terminal to assign a node address to an operational circuit, and subsequently to couple the first configuration terminal to the second configuration terminal. The integrated circuit is subsequently responsive to the node address when the node address is received.

Claims

1. An integrated circuit comprising:

a first configuration terminal;

a second configuration terminal; and

an auto addressing circuit coupled to the first and second configuration terminals, and responsive to a data pattern received at the first configuration terminal to assign a node address to an operational circuit, and subsequently to couple the first configuration terminal to the second configuration terminal, the auto addressing circuit comprising;

a comparator including a first input coupled to the first configuration terminal, a second input for receiving a reference voltage, and an output;

a repeater including an input coupled to the first configuration terminal, a control input, and an output coupled to the second configuration terminal; and

an address assignment circuit including an input coupled to the output of the comparator and a control output coupled to the control input of the repeater, the address assignment circuit configured to disable the repeater in response to receiving the data pattern and to activate the repeater after assigning the node address,

wherein the integrated circuit is subsequently responsive to the node address when the node address is received.

2. The integrated circuit of claim 1, wherein:

the data pattern includes the node address; and

the auto addressing circuit decodes the data pattern to determine and assign the node address.

3. The integrated circuit of claim 2, wherein the auto addressing circuit generates a second data pattern including a second node address and provides the second data pattern to the second configuration terminal.

4. The integrated circuit of claim 1, wherein the auto addressing circuit provides a control signal to the operational circuit having a bus terminal coupled to a bus, the control signal to enable the operational circuit to receive the node address from the bus terminal.

5. An integrated circuit comprising:

a first configuration terminal;

a second configuration terminal; and

an auto addressing circuit coupled to the first and second configuration terminals, and responsive to a data pattern received at the first configuration terminal to assign a node address to an operational circuit, and subsequently to couple the first configuration terminal to the second configuration terminal, the auto addressing circuit comprising;

a first comparator including a first input coupled to the first configuration terminal, a second input for receiving a first reference signal, and an output;

a second comparator including a first input coupled to the first configuration terminal, a second input for receiving a second reference signal, and an output; and

a repeater including an input coupled to the first configuration terminal, a control input, and an output coupled to the second configuration terminal; and

an address assignment circuit including a first input coupled to the output of the first comparator, a second input coupled to the output of the second comparator, and a control output coupled to the control input of the repeater, the address assignment circuit configured to detect the data pattern using the first comparator and to detect a failed module based on a signal strength of the data pattern using the second comparator,

wherein the integrated circuit is subsequently responsive to the node address when the node address is received.

6. An electronic module comprising:

a first configuration terminal;

a second configuration terminal;

a bus terminal;

a resistor having a first terminal coupled to the first configuration terminal, and a second terminal coupled to the second configuration terminal;

an auto addressing circuit coupled to the first and second configuration terminals, and responsive to a data pattern received at the first configuration terminal to assign a node address to an operational circuit, and subsequently to couple the first configuration terminal to the second configuration terminal through a repeater, wherein the repeater restores a signal on the first configuration terminal to an original level; and

the operational circuit is subsequently responsive to the node address when the node address is received at the bus terminal.

7. The electronic module of claim 6 wherein:

the first and second configuration terminals, the bus terminal, the auto addressing circuit, and the operational circuit are combined on an integrated circuit; and

the resistor is external to the integrated circuit.

8. The electronic module of claim 7 wherein the operational circuit comprises a sensor.

9. The electronic module of claim 6, wherein the operational circuit is coupled to the bus and is responsive to the auto addressing circuit to receive the node address at the bus terminal after the auto addressing circuit receives the data pattern.

10. The electronic module of claim 6, wherein the auto addressing circuit decodes the data pattern to determine the node address and assigns the node address to the operational circuit.

11. The electronic module of claim 6, wherein the auto addressing circuit regenerates the data pattern to include a new node address and provides the data pattern to the second configuration terminal.

12. The electronic module of claim 6, wherein the resistor provides the data pattern to the second configuration terminal when the auto addressing circuit fails.

13. The electronic module of claim 6, wherein the auto addressing circuit comprises:

a comparator including a first input coupled to the first configuration terminal, a second input for receiving a reference voltage, and an output;

the repeater including an input coupled to the first configuration terminal, a control input, and an output coupled to the second configuration terminal; and

an address assignment circuit including an input coupled to the output of the comparator and a control output coupled to the control input of the repeater, the address assignment circuit configured to disable the repeater in response to receiving the data pattern and to activate the repeater after assigning the node address.

14. The electronic module of claim 13, wherein:

the auto addressing circuit deactivates the repeater by connecting the output of the repeater to ground in response to the data pattern, and

the auto addressing circuit activates the repeater by disconnecting the output of the repeater from ground after assigning the node address.

15. The electronic module of claim 6, wherein the auto addressing circuit comprises:

a first comparator including a first input coupled to the first configuration terminal, a second input for receiving a first reference signal, and an output;

a second comparator including a first input coupled to the first configuration terminal, a second input for receiving a second reference signal, and an output; and

the repeater including an input coupled to the first configuration terminal, a control input, and an output coupled to the second configuration terminal; and

an address assignment circuit including a first input coupled to the output of the first comparator, a second input coupled to the output of the second comparator, and a control output coupled to the control input of the repeater, the address assignment circuit configured to detect the data pattern using the first comparator and to detect a failed module based on a signal strength of the data pattern using the second comparator.

16. The electronic module of claim 6, wherein the resistor provides a bypass path for providing the data pattern to a next integrated circuit in a daisy chain configuration when the auto addressing circuit fails.

17. A circuit comprising:

a first configuration terminal configurable to receive a data pattern from one of an electronic control unit and a previous circuit of a plurality of electronic modules in a daisy-chain;

a second configuration terminal configurable to float or to couple to the first configuration terminal of a next electronic module of the plurality of electronic modules in the daisy-chain;

a bus terminal configurable to couple to a common bus;

a resistor including a first terminal coupled to the first configuration terminal and a second terminal coupled to the second configuration terminal for providing a first signal path; and

an auto addressing circuit coupled to the first configuration terminal and the second configuration terminal, the auto addressing circuit configured to selectively provide a second signal path between the first configuration terminal and the second configuration terminal through a repeater, wherein the repeater restores a signal on the first configuration terminal to an original level, after receiving a node address at one of the first configuration terminal and the bus terminal.

18. The circuit of claim 17, wherein, in an active bus mode, a first electronic module of the plurality of electronic modules receives the data pattern, decodes the data pattern, and controls an operational circuit to receive the node address on the bus terminal.

19. The circuit of claim 17, wherein, in a passive bus mode, a first electronic module of the plurality of electronic modules receives the data pattern including a node address on the first configuration terminal, decodes the data pattern, and assigns the node address to an operational circuit.