Interrupt techniques

• US 8,645,596 B2
• Filed: 12/30/2008
• Issued: 02/04/2014
• Est. Priority Date: 12/30/2008
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kumar, Amit, King, Steven, Huggahalli, Ram, Zhu, Xia, Memon, Mazhar, Berry, Frank, Bhardwaj, Nitin, Willke, Theodore II
• Primary Examiner(s): Tsai, Henry
• Assistant Examiner(s): ROCHE, JOHN B
• Application Number:
  US12/319,033
• Publication Number:
  US 20100169528A1
• Time in Patent Office: 1,862 Days
• Field of Search: 710/52
• US Class Current: 710/52
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/9094 Arrangements for simultaneous transmit and receive, e.g. simultaneous reading/writing from/to the storage element

Abstract

Techniques are described that can be used by a message engine to notify a core or hardware thread of activity. For example, an inter-processor interrupt can be used to notify the core or hardware thread. The message engine may generate notifications in response to one or more message received from a transmitting message engine. Message engines may communicate without sharing memory space.

Claims

1. A method comprising:

receiving contents of a network protocol unit from one or more message segments at a buffer identified by a queue associated with a virtual message receive engine, wherein the virtual message receive engine is associated with a message engine and wherein identification of a memory address of the buffer comprises identification of a virtual message engine address of the message engine and is independent of identifying a destination memory address of the buffer, wherein at least one of the message segments comprises;

a destination virtual message engine address;

a reassembly tag field; and

a message segment offset field, wherein

the queue is based at least in part on the reassembly tag field,

the buffer is located based at least in part on the reassembly tag field, and

a location in the buffer to store at least one of the message segments is based at least in part on the message segment offset field; and

indicating availability of contents of the buffer to a core using an interrupt.

2. The method of claim 1, wherein the indicating availability of contents of the buffer from the message engine to a core using an interrupt comprises generating an inter-processor interrupt.

3. The method of claim 1, wherein the indicating availability of contents of the buffer from the message engine to a core using an interrupt comprises writing an MSI-X message in an MSI-X memory region.

4. The method of claim 1, further comprising:

the core programming a rate at which the message engine can interrupt the core.

5. The method of claim 4, wherein the core programming a rate comprises the core writing to a register in a coherent memory domain.

6. The method of claim 1, wherein the network protocol unit is Ethernet compliant.

7. The method of claim 1, wherein at least one of the message segments comprises:

a link layer; and

a data portion.

8. The method of claim 1, further comprising:

receiving an indication of a page fault in response to attempting to write contents of the one or more message segments to the buffer; and

indicating the page fault to the core using a second interrupt.

9. The method of claim 1, further comprising:

receiving a second network protocol unit;

transmitting contents of the second network protocol unit using one or more message segments to a second buffer associated with a second message engine; and

indicating availability of contents of the second buffer to a second core using a second interrupt.

25. The method of claim 8, wherein the second interrupt comprises one or more of an inter-processor interrupt and an MSI-X message.

10. An apparatus comprising:

a memory configured to store a buffer to receive contents of a network protocol unit from one or more message segments;

a core; and

a message engine to indicate availability of the contents of the buffer to the core using an interrupt, wherein the message engine is configured to associate with a virtual message receive engine and wherein identification of a memory address of the buffer includes identification of a virtual message engine address of the virtual message receive engine and is independent of identification of a destination memory address of the buffer, wherein at least one of the message segments comprises;

a destination virtual message engine address;

a reassembly tag field; and

a message segment offset field, wherein

a queue is based at least in part on the reassembly tag field,

the buffer is identified using the queue and is located based at least in part on the reassembly tag field, and

a location in the buffer to store at least one of the message segments is based at least in part on the message segment offset field.

11. The apparatus of claim 10, wherein to indicate availability of contents of the buffer from the message engine to the core, the message engine is to generate an inter-processor interrupt.

12. The apparatus of claim 10, wherein to indicate availability of contents of the buffer from the message engine to the core, the message engine is to write an MSI-X message in an MSI-X memory region.

13. The apparatus of claim 10, wherein the core is to program a rate at which the message engine is permitted to interrupt the core.

14. The apparatus of claim 13, wherein to program a rate at which the message engine is permitted to interrupt the core, the core is to write to a register in a coherent memory domain.

15. The apparatus of claim 10, wherein at least one of the message segments comprises:

a link layer; and

a data portion.

16. The apparatus of claim 10, further comprising:

a second buffer, wherein;

in response to receipt of an indication of a page fault in response to an attempt to write contents of the one or more message segments to the second buffer, the message engine is to indicate the page fault to the core using an interrupt.

17. The apparatus of claim 10, further comprising:

a second buffer to receive contents of a network protocol unit from one or more message segments, wherein to indicate availability of contents of the second buffer to the core, the message engine is to generate one or more of an inter-processor interrupt and an MSI-X message.

18. The apparatus of claim 10, wherein the core is to regulate the rate at which the core is to receive interrupts.

19. A system comprising:

a storage device;

at least one core;

a network interface to receive a network protocol unit; and

first and second message engines, wherein

the first message engine is to form at least one message from contents of the network protocol unit and to transmit the at least one message to a buffer accessible to the second message engine, wherein a virtual message receive engine is configured to associate with the second message engine and wherein to transmit to the buffer, the first message engine is to identify a memory address of the buffer using a virtual message engine address of the virtual message receive engine independent of identification of the destination memory address of the buffer, wherein at least one message comprises;

a destination virtual message engine address;

a reassembly tag field; and

a message segment offset field, wherein

a queue is based at least in part on the reassembly tag field,

the buffer is identified using the queue and is located based at least in part on the reassembly tag field, and

a location in the buffer to store at least one of the message segments is based at least in part on the message segment offset field, and

the second message engine is to notify one of the at least one core of availability of the message using an interrupt.

20. The system of claim 19, wherein to notify one of the at least one core of availability of the message using an interrupt, the second message engine is to generate one or more of an inter-processor interrupt and an MSI-X message.

21. The system of claim 19, wherein at least one core is to program a rate at which the second message engine is to generate interrupts.

22. The system of claim 19, wherein the first message engine comprises:

a message mapper to determine a destination virtual message receive engine associated with the network protocol unit; and

logic to transmit content of the network protocol unit using at least one message to a buffer associated with the destination virtual message receive engine.

23. The system of claim 19, wherein the first message engine is to form at least one segment from the at least one message.

24. The system of claim 19, wherein at least one message further comprises:

a link layer and

a data portion.