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Branch target address cache for predicting instruction decryption keys in a microprocessor that fetches and decrypts encrypted instructions

  • US 8,645,714 B2
  • Filed: 04/21/2011
  • Issued: 02/04/2014
  • Est. Priority Date: 05/25/2010
  • Status: Active Grant
First Claim
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1. A microprocessor, comprising:

  • a branch target address cache (BTAC), configured to cache history information associated with a plurality of previously executed branch and switch key instructions, wherein the history information includes a target address and an identifier for identifying key values associated with each of the previously executed branch and switch key instructions; and

    a fetch unit, coupled to the BTAC, configured to;

    receive from the BTAC a prediction that the fetch unit fetched one of the plurality of previously executed branch and switch key instructions and receive from the BTAC the target address and identifier associated with the fetched branch and switch key instruction; and

    fetch encrypted instruction data at the associated target address and decrypt the fetched encrypted instruction data based on the key values identified by the identifier, in response to receiving the prediction;

    wherein the history information further comprises a taken/not taken indicator associated with each of the plurality of previously executed branch and switch key instructions, wherein the fetch unit is configured to fetch encrypted instruction data at the associated target address and decrypt the fetched encrypted instruction data based on the key values identified by the identifier, in response to receiving the prediction only if the taken/not taken indicator received from the BTAC predicts the fetched one of the plurality of previously executed branch and switch key instructions will be taken.

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