Branch target address cache for predicting instruction decryption keys in a microprocessor that fetches and decrypts encrypted instructions

• US 8,645,714 B2
• Filed: 04/21/2011
• Issued: 02/04/2014
• Est. Priority Date: 05/25/2010
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Henry, G. Glenn, Parks, Terry, Bean, Brent, Crispin, Thomas A.
• Primary Examiner(s): Rahman, Mahfuzur
• Application Number:
  US13/091,828
• Publication Number:
  US 20110296206A1
• Time in Patent Office: 1,020 Days
• Field of Search: 713/190
• US Class Current: 713/190
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 21/52 during program execution, e.g. stack integrity ; Preventing unwanted data erasure; Buffer overflow
• CPC Class Codes: G06F 21/54 by adding security routines or objects to programs
• CPC Class Codes: G06F 21/602 Providing cryptographic facilities or services
• CPC Class Codes: G06F 21/71 to assure secure computing or processing of information
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G06F 2212/402 Encrypted data
• CPC Class Codes: G06F 2212/452 Instruction code
• CPC Class Codes: G06F 2221/2107 File encryption
• CPC Class Codes: G06F 9/30003 Arrangements for executing specific machine instructions
• CPC Class Codes: G06F 9/30058 Conditional branch instructions
• CPC Class Codes: G06F 9/30079 Pipeline control instructions, e.g. multicycle NOP
• CPC Class Codes: G06F 9/30178 of compressed or encrypted instructions
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: H04L 2209/12 Details relating to cryptographic hardware or logic circuitry
• CPC Class Codes: H04L 2209/20 Manipulating the length of blocks of bits, e.g. padding or block truncation
• CPC Class Codes: H04L 9/0618 Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
• CPC Class Codes: H04L 9/0827 involving distinctive intermediate devices or communication paths network architectures or network communication protocols using different networks H04L63/18
• CPC Class Codes: H04L 9/0861 Generation of secret information including derivation or calculation of cryptographic keys or passwords
• CPC Class Codes: H04L 9/0891 Revocation or update of secret information, e.g. encryption key update or rekeying
• CPC Class Codes: H04L 9/0894 : Escrow, recovery or storing of secret information, e.g. secret key escrow or cryptographic key storage

Abstract

A branch target address cache (BTAC) caches history information associated with branch and switch key instructions previously executed by a microprocessor. The history information includes a target address and an identifier (index into a register file) for identifying key values associated with each of the previous branch and switch key instructions. A fetch unit receives from the BTAC a prediction that the fetch unit fetched a previous branch and switch key instruction and receives the target address and identifier associated with the fetched branch and switch key instruction. The fetch unit also fetches encrypted instruction data at the associated target address and decrypts (via XOR) the fetched encrypted instruction data based on the key values identified by the identifier, in response to receiving the prediction. If the BTAC predicts correctly, a pipeline flush normally associated with the branch and switch key instruction is avoided.

Claims

1. A microprocessor, comprising:

a branch target address cache (BTAC), configured to cache history information associated with a plurality of previously executed branch and switch key instructions, wherein the history information includes a target address and an identifier for identifying key values associated with each of the previously executed branch and switch key instructions; and

a fetch unit, coupled to the BTAC, configured to;

receive from the BTAC a prediction that the fetch unit fetched one of the plurality of previously executed branch and switch key instructions and receive from the BTAC the target address and identifier associated with the fetched branch and switch key instruction; and

fetch encrypted instruction data at the associated target address and decrypt the fetched encrypted instruction data based on the key values identified by the identifier, in response to receiving the prediction;

wherein the history information further comprises a taken/not taken indicator associated with each of the plurality of previously executed branch and switch key instructions, wherein the fetch unit is configured to fetch encrypted instruction data at the associated target address and decrypt the fetched encrypted instruction data based on the key values identified by the identifier, in response to receiving the prediction only if the taken/not taken indicator received from the BTAC predicts the fetched one of the plurality of previously executed branch and switch key instructions will be taken.

2. The microprocessor of claim 1, wherein the fetch unit is configured to decrypt the fetched encrypted instruction data by performing a Boolean exclusive-OR (XOR) operation of the fetched encrypted instruction data with a decryption key generated as a function of the key values identified by the identifier.

3. The microprocessor of claim 1, wherein the BTAC is further configured to cache history information associated with a plurality of previously executed conventional branch instructions, wherein the history information associated with both branch and switch key instructions and conventional branch instructions includes a type indicator for indicating whether the branch instruction is a branch and switch key instruction or a conventional branch instruction.

4. The microprocessor of claim 1, wherein the fetch unit is configured to generate a fetch address at which to fetch instruction data from an instruction cache, wherein the fetch address is also used to access the BTAC.

5. The microprocessor of claim 1, wherein the microprocessor is configured to avoid flushing its pipeline if the microprocessor subsequently determines that the BTAC correctly predicted the fetched one of the plurality of previously executed branch and switch key instructions.

6. The microprocessor of claim 1, wherein if the microprocessor executes a branch and switch key instruction and determines that the BTAC failed to predict that the fetch unit fetched the branch and switch key instruction, the microprocessor is configured to:

flush its pipeline;

fetch encrypted instruction data at a target address specified by the branch and switch key instruction; and

decrypt the fetched encrypted instruction data using key values specified by the branch and switch key instruction.

7. A microprocessor, comprising:

a branch target address cache (BTAC), configured to cache history information associated with a plurality of previously executed branch and switch key instructions, wherein the history information includes a target address and an identifier for identifying key values associated with each of the previously executed branch and switch key instructions, wherein the identifier comprises an index into a location within a register file configured to store the key values;

a fetch unit, coupled to the BTAC, configured to;

receive from the BTAC a prediction that the fetch unit fetched one of the plurality of previously executed branch and switch key instructions and receive from the BTAC the target address and identifier associated with the fetched branch and switch key instruction; and

fetch encrypted instruction data at the associated target address and decrypt the fetched encrypted instruction data based on the key values identified by the identifier, in response to receiving the prediction;

wherein the fetch unit further comprises;

a master key register file, configured to store a plurality of key values used by the fetch unit to decrypt fetched encrypted instruction data; and

key switch logic, coupled to the BTAC and to the master key register file, configured to update the master key register file with the key values stored in the location within the register file at the index received from the BTAC.

8. The microprocessor of claim 7, wherein the microprocessor is configured to subsequently restore the master key register file key values to their pre-updated state if the BTAC incorrectly predicted the one of the plurality of previously executed branch and switch key instructions.

9. A microprocessor comprising:

a branch target address cache (BTAC), wherein the BTAC is configured to cache history information associated with a plurality of previously executed switch key instructions, wherein the history information includes a target address and an identifier for identifying key values associated with each of the previously executed switch key instructions, wherein the history information associated with both branch and switch key instructions and switch key instructions specifies a type indication for indicating whether the branch instruction is a branch and switch key instruction or a switch key instruction; and

a fetch unit, coupled to the BTAC, configured to;

receive from the BTAC a prediction that the fetch unit fetched one of the plurality of previously executed branch and switch key instructions and receive from the BTAC the target address and identifier associated with the fetched branch and switch key instruction; and

fetch encrypted instruction data at the associated target address and decrypt the fetched encrypted instruction data based on the key values identified by the identifier, in response to receiving the prediction.

10. A method for operating a microprocessor, the method comprising:

caching history information associated with a plurality of previously executed branch and switch key instructions in a branch target address cache (BTAC), wherein the history information includes a target address and an identifier for identifying key values associated with each of the previously executed branch and switch key instructions, wherein the history information further comprises a taken/not taken indicator associated with each of the plurality of previously executed branch and switch key instructions;

receiving from the BTAC a prediction that one of the plurality of previously executed branch and switch key instructions was fetched and receiving the target address and identifier associated with the fetched branch and switch key instruction; and

fetching encrypted instruction data at the associated target address and decrypting the fetched encrypted instruction data based on the key values identified by the identifier, in response to said receiving the prediction only if the taken/not taken indicator received from the BTAC predicts the fetched one of the plurality of previously executed branch and switch key instructions will be taken.

11. The method of claim 10, wherein said decrypting the fetched encrypted instruction data comprises performing a Boolean exclusive-OR (XOR) operation of the fetched encrypted instruction data with a decryption key generated as a function of the key values identified by the identifier.

12. The method of claim 10, further comprising:

caching in the BTAC history information associated with a plurality of previously executed conventional branch instructions, wherein the history information associated with both branch and switch key instructions and conventional branch instructions includes a type indicator for indicating whether the branch instruction is a branch and switch key instruction or a conventional branch instruction.

13. The method of claim 10, further comprising:

generating a fetch address at which to fetch instruction data from an instruction cache; and

accessing the BTAC with the fetch address.

14. The method of claim 10, further comprising:

refraining from flushing a pipeline of the microprocessor if the microprocessor subsequently determines that the BTAC correctly predicted the fetched one of the plurality of previously executed branch and switch key instructions.

15. The method of claim 10, further comprising:

executing a branch and switch key instruction;

in response to determining that the BTAC failed to predict that the fetch unit fetched the branch and switch key instruction;

flushing a pipeline of the microprocessor;

fetching encrypted instruction data at a target address specified by the branch and switch key instruction; and

decrypting the fetched encrypted instruction data using key values specified by the branch and switch key instruction.

16. A method for operating a microprocessor, the method comprising:

storing in a master key register file a plurality of key values used to decrypt fetched encrypted instruction data;

caching history information associated with a plurality of previously executed branch and switch key instructions in a branch target address cache (BTAC), wherein the history information includes a target address and an identifier for identifying key values associated with each of the previously executed branch and switch key instructions, wherein the identifier comprises an index into a location within a register file configured to store key values;

receiving from the BTAC a prediction that one of the plurality of previously executed branch and switch key instructions was fetched and receiving the target address and identifier associated with the fetched branch and switch key instruction;

updating the master key register file with the key values stored in the location within the register file at the index received from the BTAC, in response to said receiving the prediction; and

fetching encrypted instruction data at the associated target address and decrypting the fetched encrypted instruction data based on the key values identified by the identifier, in response to said receiving the prediction.

17. The method of claim 16, further comprising:

subsequently restoring the master key register file key values to their pre-updated state if the BTAC incorrectly predicted the one of the plurality of previously executed branch and switch key instructions.

18. A method for operating a microprocessor, the method comprising:

caching history information associated with a plurality of previously executed branch and switch key instructions in a branch target address cache (BTAC), wherein the history information includes a target address and an identifier for identifying key values associated with each of the previously executed branch and switch key instructions; and

wherein the history information associated with both branch and switch key instructions and switch key instructions specifies a type indication for indicating whether the branch instruction is a branch and switch key instruction or a switch key instruction

receiving from the BTAC a prediction that one of the plurality of previously executed branch and switch key instructions was fetched and receiving the target address and identifier associated with the fetched branch and switch key instruction; and

fetching encrypted instruction data at the associated target address and decrypting the fetched encrypted instruction data based on the key values identified by the identifier, in response to said receiving the prediction.

19. A computer program product encoded in at least one non-transitory computer readable storage medium for use with a computing device, the computer program product comprising:

computer readable program code embodied in said medium, for specifying a microprocessor, the computer readable program code comprising;

first program code for specifying a branch target address cache (BTAC), configured to cache history information associated with a plurality of previously executed branch and switch key instructions, wherein the history information includes a target address and an identifier for identifying key values associated with each of the previously executed branch and switch key instructions; and

second program code for specifying a fetch unit, coupled to the BTAC, configured to;

receive from the BTAC a prediction that the fetch unit fetched one of the plurality of previously executed branch and switch key instructions and receive from the BTAC the target address and identifier associated with the fetched branch and switch key instruction; and

fetch encrypted instruction data at the associated target address and decrypt the fetched encrypted instruction data based on the key values identified by the identifier, in response to receiving the prediction;

wherein the history information further comprises a taken/not taken indicator associated with each of the plurality of previously executed branch and switch key instructions, wherein the fetch unit is configured to fetch encrypted instruction data at the associated target address and decrypt the fetched encrypted instruction data based on the key values identified by the identifier, in response to receiving the prediction only if the taken/not taken indicator received from the BTAC predicts the fetched one of the plurality of previously executed branch and switch key instructions will be taken.

20. The computer program product of claim 19, wherein the at least one non-transitory computer readable storage medium is selected from a set of a disk, tape, or other magnetic, optical, or electronic storage medium.