Scalable I/O adapter function level error detection, isolation, and reporting

• US 8,645,767 B2
• Filed: 06/23/2010
• Issued: 02/04/2014
• Est. Priority Date: 06/23/2010
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Craddock, David F., Gregg, Thomas A., Lais, Eric N.
• Primary Examiner(s): MCCARTHY, CHRISTOPHER S
• Application Number:
  US12/821,247
• Publication Number:
  US 20110320887A1
• Time in Patent Office: 1,322 Days
• Field of Search: None
• US Class Current: 714/43
• CPC Class Codes: G06F 11/0745 in an input/output transactions management context input/output processing in general G06F13/00
• CPC Class Codes: G06F 11/0766 Error or fault reporting or storing
• CPC Class Codes: G06F 11/0775 Content or structure details of the error report, e.g. specific table structure, specific error fields

Abstract

Embodiments of the invention relate to scalable input/output (I/O) function level error detection, isolation, and reporting. An error is detected in a communication initiated between a function and the system memory, the communication including an I/O request from an application. Future communication between the function and the system memory is prevented in response to the detecting. The application is notified that the error in communication occurred in response to the detecting.

Claims

1. A system for implementing scalable input/output (I/O) function level error detection, isolation, and reporting, the system comprising:

an I/O hub communicatively coupled to a computer processor, system memory and at least one I/O adapter, the at least one I/O adapter including a function and the I/O hub including logic for implementing a method, the method comprising;

detecting an error in a communication initiated between the function and the system memory, the communication including an I/O request from an application;

preventing future communication between the function and the system memory in response to the detecting;

notifying the application that the error in communication occurred in response to the detecting; and

creating an error entry in the system memory in response to the detecting, the error entry identifying the function in error and a specific error condition detected by the I/O hub,

wherein the error entry is written to a location in the system memory specified as an offset from an error log base address, and wherein the offset is based on an identification number of the at least one I/O adapter.

2. The system of claim 1, wherein the I/O hub is communicatively coupled to the computer processor and the system memory via a Peripheral Component Interconnect Express (PCIe) bus.

3. The system of claim 1, wherein the I/O hub sets a flag in the system memory indicating that the one of the one or more I/O adapters is in an error state in response to the detecting, and sends an interrupt to the computer processor, the interrupt causing a monitoring thread to initialize and check the status of the flag.

4. The system of claim 3 wherein the notifying is responsive to the monitoring thread detecting that the flag indicates that the I/O adapter is in an error state.

5. The system of claim 1 wherein one or more bits are set in the I/O hub to indicate that one of the one or more I/O adapters has entered an error state in response to the detecting.

6. The system of claim 5 wherein the I/O hub prevents the future communication between the function and the system memory in response to checking the single bit before processing a transaction from the I/O adapter.

7. The system of claim 1, wherein the detected error comprises at least one of:

receiving an address outside of a range registered for the at least one I/O adapter;

an address translation error;

an interrupt processing error; and

a Peripheral Component Interconnect (PCI) fatal error.

8. The system of claim 1, wherein the offset is further based on a product of the identification number of the at least one I/O adapter, a number of words allocated for each of a plurality of error entries in the system memory, and a number of bits in each word.

9. The system of claim 1, wherein the error entry further identifies:

data received during the error in communication;

a length of the communication in error;

an indication of whether the communication in error is a read operation or a write operation; and

a virtual address of the at least one I/O adapter which indicates an address being processed by the I/O hub when the error is detected.

10. A computer program product for implementing scalable input/output (I/O) function level error detection, isolation, and reporting, the computer program product comprising:

a non-transitory storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising;

detecting, via an I/O hub, an error in a communication initiated between a function and a system memory, the communication including an I/O request from an application, and the function executing on an I/O adapter;

preventing future communication between the function and the system memory in response to the detecting;

notifying the application that the error in communication occurred in response to the detecting; and

creating an error entry in the system memory in response to the detecting, the error entry identifying the function in error and a specific error condition detected by the I/O hub,

wherein the error entry is written to a location in the system memory specified as an offset from an error log base address, and wherein the offset is based on an identification number of the I/O adapter.

11. The computer program product of claim 10, wherein the I/O adapter is a Peripheral Component Interconnect Express (PCIe) adapter.

12. The computer program product of claim 10, wherein the I/O hub sets a flag in the system memory indicating that one of the one or more I/O adapters is in an error state in response to the detecting, and sends an interrupt to a computer processor, the interrupt causing a monitoring thread to initialize and check the status of the flag.

13. The computer program product of claim 12 wherein the notifying is responsive to the monitoring thread detecting that the flag indicates that the I/O adapter is in an error state.

14. The computer program product of claim 10 wherein one or more bits are set in the I/O hub to indicate that one of the one or more I/O adapters has entered an error state in response to the detecting.

15. The computer program product of claim 14 wherein the I/O hub prevents the future communication between the function and the system memory in response to checking the single bit before processing a transaction from the I/O adapter.

16. The computer program product of claim 10, wherein the detected error comprises at least one of:

receiving an address outside of a range registered for the I/O adapter;

an address translation error;

an interrupt processing error; and

a Peripheral Component Interconnect (PCI) fatal error.

17. The computer program product of claim 10, wherein the offset is further based on a product of the identification number of the I/O adapter, a number of words allocated for each of a plurality of error entries in the system memory, and a number of bits in each word.

18. The computer program product of claim 10, wherein the error entry further identifies:

data received during the error in communication;

a length of the communication in error;

an indication of whether the communication in error is a read operation or a write operation; and

a virtual address of the I/O adapter which indicates an address being processed by the I/O hub when the error is detected.