Data storage in analog memory cells using a non-integer number of bits per cell

• US 8,645,794 B1
• Filed: 07/28/2011
• Issued: 02/04/2014
• Est. Priority Date: 07/31/2010
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Meir, Avraham, Anholt, Micha, Sommer, Naftali, Gurgi, Eyal
• Primary Examiner(s): Abraham, Esaw
• Application Number:
  US13/192,495
• Time in Patent Office: 922 Days
• Field of Search: 714/763, 365/185.03, 365/185.18
• US Class Current: 714/763
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 2211/5647 Multilevel memory with bit inversion arrangement
• CPC Class Codes: G11C 2211/5648 Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS

Abstract

A method for data storage includes, in a first programming phase, storing first data in a group of analog memory cells by programming the memory cells in the group to a set of initial programming levels. In a second programming phase that is subsequent to the first programming phase, second data is stored in the group by: identifying the memory cells in the group that were programmed in the first programming phase to respective levels in a predefined partial subset of the initial programming levels; and programming only the identified memory cells with the second data, so as to set at least some of the identified memory cells to one or more additional programming levels that are different from the initial programming levels.

Claims

1. A method for data storage, comprising:

in a first programming phase, storing first data in a first plurality of analog memory cells, wherein storing the first data includes programming each analog memory cell of the first plurality of analog memory cells to a given one of a set of initial programming levels dependent upon the first data; and

in a second programming phase, that is subsequent to the first programming phase, storing second data in the plurality of analog memory cells wherein storing the second data includes;

reading the stored first data in each analog memory cell of the plurality of analog memory cells;

identifying, dependent upon the read stored first data, analog memory cells of the first plurality of analog memory cells that were programmed, in the first programming phase, to a level included in a designated partial subset of the set of initial programming levels; and

programming at least one of the identified analog memory cells to a given one of one or more additional programming levels dependent upon the second data, wherein each one of the one or more additional programming levels is different from each one of the set of initial programming levels.

2. The method according to claim 1, wherein a number of the initial programming levels is an integer power of two, and wherein an aggregate number of the initial programming levels and the additional programming levels is not an integer power of two.

3. The method according to claim 1, wherein a size of the second data is smaller than the size of the first data.

4. The method according to claim 1, further comprising performing at least one storage operation in a second plurality of analog memory cells, which neighbors the first plurality of analog memory cells, after the first programming phase and before the second programming phase.

5. The method according to claim 1, wherein storing the first data comprises pre-processing the first data before storing the first data, so as to cause at least a predefined percentage of the analog memory cells in the first plurality of analog memory cells to be programmed to the predefined partial subset of the programming levels.

6. The method according to claim 5, wherein pre-processing the first data comprises inverting the bit values of the first data upon detecting that less than the predefined percentage of the memory cells are to be programmed to the predefined partial subset of the programming levels.

7. The method according to claim 6, wherein pre-processing the first data comprises storing an inversion indication, which specifies whether the bit values have been inverted.

8. The method according to claim 7, wherein reading the stored first data includes reading the inversion indication, and inverting the bit values of the read first data when the inversion indication specifies that the bit values have been inverted.

9. The method according to claim 7, wherein storing the inversion indication comprises storing the inversion indication in at least one analog memory cell included in the first plurality of analog memory cells.

10. The method according to claim 7, wherein storing the inversion indication comprises storing the inversion indication in at least one analog memory cell that is not included in the first plurality of analog memory cells.

11. The method according to claim 6, wherein pre-processing the first data comprises setting a given bit of the first data to a fixed predefined value and encoding the first data, including the given bit, with an Error Correction Code (ECC).

12. The method according to claim 11, wherein reading the stored first data includes decoding the ECC so as to produce ECC-decoded first data, and inverting the bit values of the ECC-decoded first data when the bit value of the decoded given bit differs from the fixed predefined value.

13. The method according to claim 5, wherein pre-processing the first data comprises pre-processing the first data before encoding the pre-processed first data with an Error Correction Code (ECC).

14. The method according to claim 5, wherein pre-processing the first data comprises scrambling the first data with a scrambling seed that is selected to cause at least the predefined percentage of the memory cells to be programmed to the predefined partial subset of the programming levels.

15. The method according to claim 5, wherein pre-processing the first data comprises choosing the predefined subset of the programming levels such that at least the predefined percentage of the memory cells are programmed in the first programming phase to the partial subset.

16. The method according to claim 1, and comprising skipping the second programming phase upon detecting that less than a predefined percentage of the analog memory cells in the first plurality of analog memory cells are programmed in the first programming phase to the predefined partial subset of the programming levels.

17. The method according to claim 1, wherein storing the first data comprises encoding the first data with an Error Correction Code (ECC), and comprising reading the second data from the group of memory cells by:

reading the stored first data from the first plurality of analog memory cells and decoding the ECC, to produce ECC-decoded first data;

based on the ECC-decoded first data, identifying the memory cells in the first plurality of analog memory cells in which the second data is stored; and

reading the second data only from the first plurality of analog memory cells identified based on the ECC-decoded first data.

18. The method according to claim 1, wherein storing the first and second data comprises programming the memory cells in the group using a Gray mapping of bit value combinations to programming levels.

19. The method according to claim 1, wherein storing the second data comprises storing an indication that the first data stored in one or more of analog memory cells in the first plurality of analog memory cells is subject to distortion.

20. The method according to claim 1, and comprising defining the initial programming levels, the predefined subset of the initial programming levels and the additional programming levels jointly for a set of two or more of the analog memory cells.

21. An apparatus for data storage, comprising:

a memory, wherein the memory includes an array of analog memory cells; and

storage circuitry, which is configured to;

store first data in a first portion of the array of analog memory cells in a first programming phase, wherein to store the first data the storage circuitry is further configured to program each analog memory cell of the first portion of the array memory cells to a given one of a set of initial programming levels dependent upon the first data; and

in a second programming phase that is subsequent to the first programming phase, store second data in the portion of the array of analog memory cells, wherein to store the second data, the storage circuit is further configured to;

reading the stored first data from each analog memory cell of the portion of the array of analog memory cells;

identify, dependent upon the read stored data, analog memory cells included in the portion of the array of analog memory cells that were programmed, in the first programming phase, to a level included in a designated partial subset of the set initial programming levels; and

program at least one of the identified memory cells to a given one of one or more additional programming levels dependent upon the second data, wherein each one of the one or more additional programming levels is different from each one of the set initial programming levels.

22. The apparatus according to claim 21, wherein a number of the initial programming levels is an integer power of two, and wherein an aggregate number of the initial programming levels and the additional programming levels is not an integer power of two.

23. The apparatus according to claim 21, wherein a size of the second data is smaller than the size of the first data.

24. The apparatus according to claim 21, wherein the storage circuitry is further configured to perform at least one storage operation in second portion of the array of analog memory cells, which neighbors the first portion of the array of analog memory cells, after the first programming phase and before the second programming phase.

25. The apparatus according to claim 21, wherein the storage circuitry is further configured to pre-process the first data before storing the first data, so as to cause at least a predefined percentage of the first portion of the array of analog memory cells to be programmed to the predefined partial subset of the programming levels.

26. The apparatus according to claim 25, wherein the storage circuitry is further configured to invert the bit values of the first data upon detecting that less than the predefined percentage of the first portion of the array of analog memory cells are to be programmed to the predefined partial subset of the programming levels.

27. The apparatus according to claim 26, wherein the storage circuitry is further configured to store an inversion indication, which specifies whether the bit values have been inverted.

28. The apparatus according to claim 27, to read the stored first data from the first portion of the array of analog memory cells, the storage circuit is further configured to read the inversion indication, and to invert the bit values of the read first data when the inversion indication specifies that the bit values have been inverted.

29. The apparatus according to claim 27, wherein the storage circuitry is further configured to store the inversion indication in at least one memory cell belonging to the group.

30. The apparatus according to claim 27, wherein the storage circuitry is further configured to store the inversion indication in at least one analog memory cell that is not included in the first portion of the array of analog memory cells.

31. The apparatus according to claim 26, wherein the storage circuitry is further configured to set a given bit of the first data to a fixed predefined value and to encode the first data, including the given bit, with an Error Correction Code (ECC).

32. The apparatus according to claim 31, wherein the storage circuitry is further configured to read the first data from the portion of the array of analog memory cells, to decode the ECC so as to produce ECC-decoded first data, and to invert the bit values of the ECC-decoded first data when the bit value of the decoded given bit differs from the fixed predefined value.

33. The apparatus according to claim 25, wherein the storage circuitry is further configured to pre-process the first data before encoding the pre-processed first data with an Error Correction Code (ECC).

34. The apparatus according to claim 25, wherein the storage circuitry is further configured to scramble the first data with a scrambling seed that is selected to cause at least the predefined percentage of the first portion of the array of analog memory cells to be programmed to the predefined partial subset of the programming levels.

35. The apparatus according to claim 25, wherein the storage circuitry is further configured to choose the predefined subset of the programming levels such that at least the predefined percentage of the first portion of the array of analog memory cells are programmed in the first programming phase to the partial subset.

36. The apparatus according to claim 21, wherein the storage circuitry is configured to skip the second programming phase upon detecting that less than a predefined percentage of the first portion of the array of analog memory cells in the group are programmed in the first programming phase to the predefined partial subset of the programming levels.

37. The apparatus according to claim 21, wherein the storage circuitry is configured to encode the first data with an Error Correction Code (ECC) before storing the first data, and to read the second data from the first portion of the array of analog memory cells by reading the first data from the first portion of the array of analog memory cells and decoding the ECC so as to produce ECC-decoded first data, identifying, based on the ECC-decoded first data, analog memory cells in the first portion of the array of analog memory cells in which the second data is stored, and reading the second data only from the first portion of the array of analog memory cells identified based on the ECC-decoded first data.

38. The apparatus according to claim 21, wherein the storage circuitry is further configured to program the memory cells in the group using a Gray mapping of bit value combinations to programming levels.

39. The apparatus according to claim 21, wherein the second data comprises an indication that the first data stored in one or more of the memory cells in the first portion of the array of analog memory cells is subject to distortion.

40. The apparatus according to claim 21, wherein the initial programming levels, the predefined subset of the initial programming levels and the additional programming levels are defined jointly for a set of two or more of the analog memory cells in the first portion of the array of analog memory cells.