Interconnection techniques

• US 8,645,804 B2
• Filed: 10/08/2012
• Issued: 02/04/2014
• Est. Priority Date: 03/09/2009
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ganga, Ilango, Mellitz, Richard
• Primary Examiner(s): Lamarre, Guy
• Application Number:
  US13/646,872
• Publication Number:
  US 20130031445A1
• Time in Patent Office: 484 Days
• Field of Search: 714/776, 714/752, 370/470, 370/510, 370/536
• US Class Current: 714/776
• CPC Class Codes: H03M 13/05 using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits H03M13/2906 takes precedence
• CPC Class Codes: H03M 13/13 Linear codes
• CPC Class Codes: H04L 1/0052 Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables
• CPC Class Codes: H04L 25/14 Channel dividing arrangements , i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
• CPC Class Codes: H04L 25/40 Transmitting circuits; Receiving circuits repeater circuits, relay circuits H04L25/20
• CPC Class Codes: H04L 5/1446 of transmission speed
• CPC Class Codes: H05K 7/1439 Back panel mother boards

Abstract

Techniques are described that can be used to extend the data transmission rate specified by 10GBASE-KR of IEEE 802.3ap (2007) to more than 10 Gb/s using a multiple lane backplane. A signal for transmission over 10 Gb/s can be divided into multiple streams for transmission over multiple lanes. Multiple transceiver pairs can be used for transmission and receipt of the multiple streams. Each transceiver pair may comply with 10GBASE-KR of IEEE 802.3ap (2007).

Claims

1. A forward error correction (FEC) decoder comprising:

circuitry to receive signals;

circuitry to decode data received from the signals;

circuitry to determine whether decoded data includes errors; and

circuitry configured to indicate decoding error in response to a determination that the decoded data includes errors, wherein to indicate decoding error, the circuitry is to use sync bits in at least every other transmitted block, wherein to indicate error, the circuitry is to use sync bits in at least first (1^st), third (3^rd), and fifth (5^th) blocks.

2. The decoder of claim 1, wherein to indicate decoding error, the circuitry is to set the sync bits to a value of 11 to cause associated data to be indicated as invalid.

3. The decoder of claim 1, wherein to indicate decoding error, the circuitry is to indicate error using sync bits in at least every other block transmitted to a Physical Coding Sublayer (PCS) circuitry.

4. The decoder of claim 1, wherein to indicate decoding error, the circuitry is to indicate error using sync bits in a synchronization header.

5. The decoder of claim 1, wherein the blocks comprise 64B/66B blocks.

6. A physical layer unit comprising:

a Physical Medium Dependent (PMD) sublayer interface circuitry;

a Physical Medium Attachment (PMA) sublayer circuitry communicatively coupled to the PMD sublayer circuitry;

a Forward Error Correction (FEC) decoder communicatively coupled to the PMA sublayer circuitry, the FEC decoder to receive signals and determine whether decoded data from the signals includes errors and to indicate decoding error in response to a determination that the decoded data includes errors, wherein the decoder is to indicate decoding error using sync bits in at least every other transmitted block, wherein to indicate error, the decoder is to use sync bits in at least first (1^st), third (3^rd), and fifth (5^th) blocks; and

a Physical Coding Sublayer (PCS) circuitry communicatively coupled to the FEC decoder.

7. The physical layer unit of claim 6, wherein to indicate error using sync bits in at least every other transmitted block, the FEC decoder is to set the sync bits to a value of 11 to cause associated data to be indicated as invalid.

8. The physical layer unit of claim 6, wherein the FEC decoder is to indicate error using sync bits in at least every other block transmitted to the PCS circuitry.

9. The physical layer unit of claim 6, wherein the FEC decoder is to indicate error using sync bits in a synchronization header.

10. The physical layer unit of claim 6, wherein the blocks comprise 64B/66B blocks.

11. A line card comprising:

an interface to a backplane, that when connected to a backplane is to at least receive signals from the backplane and

a Forward Error Correction (FEC) decoder communicatively coupled to the interface, the FEC decoder to receive signals and determine whether decoded data from the signals includes errors and to indicate decoding error in response to a determination that the decoded data includes errors, wherein the decoder is to indicate error using sync bits in at least every other transmitted block, wherein to indicate error, the decoder is to use sync bits in at least first (1^st), third (3^rd), and fifth (5^th) blocks.

12. The line card of claim 11, wherein to indicate error using sync bits in at least every other block, the FEC decoder is to set the sync bits to a value of 11 to cause associated data to be indicated as invalid.

13. The line card of claim 11, further comprising Physical Coding Sublayer (PCS) circuitry, wherein the FEC decoder is to indicate error using sync bits in at least every other block transmitted to the PCS circuitry.

14. The line card of claim 11, wherein the FEC decoder is to indicate error in sync bits using a synchronization header.

15. The line card of claim 11, wherein the blocks comprise 64B/66B blocks.

16. A computer-implemented method comprising:

performing forward error correction decoding on received signals;

determining whether decoded data includes errors; and

indicating error using sync bits in at least every other transmitted block in response to a determination that the decoded data includes errors, wherein the indicating error using sync bits comprises indicating error using sync bits in at least first (1^st), third (3^rd), and fifth (5^th) blocks.

17. The method of claim 16, wherein indicating error using sync bits in at least every other transmitted block comprises setting the sync bits to a value of 11 to cause associated data to be indicated as invalid.

18. The method of claim 16, further comprising indicating error using sync bits in at least every other block transmitted to a PCS sublayer.

19. The method of claim 16, wherein the indicating error using sync bits comprises indicating error using sync bits in at least one synchronization header.

20. The method of claim 16, wherein the blocks comprise 64B/66B blocks.