Porting a circuit design from a first semiconductor process to a second semiconductor process

• US 8,645,878 B1
• Filed: 08/22/2012
• Issued: 02/04/2014
• Est. Priority Date: 08/23/2011
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: SuVolta, Inc.
• Inventors: Clark, Lawrence T., Thompson, Scott E., Roy, Richard S., Leshner, Samuel
• Primary Examiner(s): Memula, Suresh
• Application Number:
  US13/592,122
• Time in Patent Office: 531 Days
• Field of Search: 716/51, 716/52, 716/54
• US Class Current: 716/54
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: H01L 21/22 Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

Porting a first integrated circuit design targeted for implementation in a first semiconductor manufacturing process, and implementing a second circuit design in a second semiconductor manufacturing process wherein the electrical performance of the second integrated circuit meets or exceeds the requirements of the first integrated circuit design even if the threshold voltage targets of the second integrated circuit design are different from those of the first integrated circuit design; and wherein physical layouts, and in particular the gate-widths and gate-lengths of the transistors, of the first and second integrated circuit designs are the same or substantially the same. The second integrated circuit design, when fabricated in the second semiconductor manufacturing process and then operated, experiences less off-state transistor leakage current than does the first integrated circuit design, when fabricated in the first semiconductor manufacturing process, and then operated. Porting includes determining processing targets for the second semiconductor manufacturing process.

Claims

1. A method of fabricating an integrated circuit, the integrated circuit including a bit cell having a plurality of physical transistors, wherein the bit cell is an implementation of a first bit cell design initially designed for a first semiconductor process, wherein the first bit cell design is migrated to a second semiconductor process, the method comprising:

a) determining the sizes of transistor representations in said first bit cell design, each of the transistors having a threshold voltage;

b) determining goals for at least one of read static noise margin, write margin, read current, and cell leakage of the first bit cell design;

c) selecting weights for each of the at least one of goals, the weights being associated with an objective function for optimization;

d) determining a gradient of the at least one of goals as a function of a device target for each transistor;

e) determining whether all of the goals have been achieved for the device target for each transistor;

f) applying a gradient step to reduce the objective function if the at least one of goals at step (e) were not achieved and repeating steps (b) through (e);

g) providing the device targets to the transistors for the second semiconductor manufacturing process if the at least one of goals at step (e) were achieved; and

h) fabricating the integrated circuit based upon process parameters in the second semiconductor process, the process parameters being determined by the device targets.

2. The method of claim 1, wherein said device target for transistors is threshold voltage.

3. The method of claim 1, further including the step of selectively doping the substrate to the dopant concentrations selected to achieve the target threshold voltages for each of the transistors, the doping forming doped regions.

4. The method of claim 3, further including the step of forming a substantially undoped semiconductor channel layer above the doped regions.

5. The method of claim 1, further including the step of determining goals for retention voltage.

6. The method of claim 1, wherein the second semiconductor manufacturing process is a DDC transistor fabrication process.

7. The method of claim 6, further comprising determining targets for a width and a length of each DDC transistor.

8. The method of claim 7, further comprising selectively doping the DDC transistors to dopant concentrations that are associated with achieving the threshold voltage values for each of the DDC transistors so as to form selectively doped regions.

9. The method of claim 8, wherein selectively doping the DDC transistors further includes using a mask pattern that is designed based upon the optimized width and length of the DDC transistors.

10. The method of claim 1, wherein each of said transistors in the hit cell is a DDC transistor.

11. The method of claim 1, wherein the hit cell includes DDC transistors for the N-FETs only.