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Method and system for model-based design and layout of an integrated circuit

  • US 8,645,887 B2
  • Filed: 06/27/2012
  • Issued: 02/04/2014
  • Est. Priority Date: 06/05/2008
  • Status: Active Grant
First Claim
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1. A computer implemented method for building a fast model to implement routing for an electronic design, comprising:

  • using at least one processor to perform a process, the process comprising;

    performing manufacturing aware analysis upon a layout to identify one or more patterns associated with the layout that correspond to one or more good or bad patterns to verify or improve at least a portion of the layout with a physical electronic design implementation tool, rather than using a separate circuit verification tool, during physical implementation of the layout with the physical electronic design implementation tool, whereinthe one or more patterns correspond to post-routing layout objects in the layout;

    generating one or more libraries of the patterns, the one or more libraries to be used by a physical electronic design implementation tool to implement the layout of an electronic design; and

    storing the one or more libraries into a non-transitory computer readable medium.

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