Method and system for model-based design and layout of an integrated circuit

• US 8,645,887 B2
• Filed: 06/27/2012
• Issued: 02/04/2014
• Est. Priority Date: 06/05/2008
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Lai, Ya-Chieh, Gennari, Frank E., Moskewicz, Matthew, Doddi, Srinivas, Lei, Junjiang, Fang, Weiping, Lay, Kuanghao
• Primary Examiner(s): Memula, Suresh
• Application Number:
  US13/535,242
• Publication Number:
  US 20120272201A1
• Time in Patent Office: 587 Days
• Field of Search: 716/110
• US Class Current: 716/110
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.

Claims

1. A computer implemented method for building a fast model to implement routing for an electronic design, comprising:

using at least one processor to perform a process, the process comprising;

performing manufacturing aware analysis upon a layout to identify one or more patterns associated with the layout that correspond to one or more good or bad patterns to verify or improve at least a portion of the layout with a physical electronic design implementation tool, rather than using a separate circuit verification tool, during physical implementation of the layout with the physical electronic design implementation tool, wherein

the one or more patterns correspond to post-routing layout objects in the layout;

generating one or more libraries of the patterns, the one or more libraries to be used by a physical electronic design implementation tool to implement the layout of an electronic design; and

storing the one or more libraries into a non-transitory computer readable medium.

2. The computer implemented method of claim 1, in which the one or more libraries comprise an exact library which comprises a set of patterns that will be exactly matched during analysis of the electronic design.

3. The computer implemented method of claim 1, in which a hash function is employed to implement the exact library.

4. The computer implemented method claim 1, in which the one or more libraries comprise an inexact library which comprises a set of patterns that does not have to be exactly matched during analysis of an electronic design.

5. The computer implemented method of claim 4, in which a neural net is employed to implement the inexact library.

6. The computer implemented method claim 1, in which the one or more libraries comprise a known good pattern library and a known bad pattern library.

7. The computer implemented method of claim 1, in which retargeting is employed to generate data for pattern extraction.

8. The computer implemented method of claim 1, in which a lossy reduction is employed to reduce data quantity for storage in the one or more libraries.

9. The computer implemented method of claim 1, in which the manufacturing aware analysis is used to generate a score for a portion of the layout.

10. The computer implemented method of claim 1, in which a set of scores is generated, wherein the set of scores comprises scores only for hotspots, scores only for good patterns, or scores for all analyzed patterns.

11. A system for routing an electronic design, comprising:

at least one processor that is to;

perform manufacturing aware analysis upon a layout to identify one or more patterns associated with the layout that correspond to one or more good or bad patterns to verify or improve at least a portion of the layout with a physical electronic design implementation tool, rather than using a separate circuit verification tool, during physical implementation of the layout with the physical electronic design implementation tool, wherein

the one or more patterns correspond to post-routing layout objects;

generate one or more libraries of the patterns, the one or more libraries to be used by a physical electronic design implementation tool to implement the layout of an electronic design; and

store the one or more libraries into a non-transitory computer readable medium.

12. The system of claim 11, in which the one or more libraries comprise an exact library which comprises a set of patterns that will be exactly matched during analysis of the electronic design.

13. The system of claim 11, in which the one or more libraries comprise an inexact library which comprises a set of patterns that does not have to be exactly matched during analysis of an electronic design.

14. The system of claim 11, in which the at least one processor is further to:

generate data for pattern extraction by using a retargeting technique.

15. The system of claim 14, in which the at least one processor that is to generate data by using the retargeting technique is further to:

mimic or recreate of an existing design flow for replicate a processing result or a simulation result of the existing design flow.

16. A computer program product comprising a non-transitory computer accessible storage medium having stored thereupon a sequence of instructions which, when executed by at least one processor, causes the at least one processor to execute a method for routing an electronic design, the method comprising:

using at least one processor to perform a process, the process comprising;

performing manufacturing aware analysis upon a layout to identify one or more patterns associated with the layout that correspond to one or more good or bad patterns to verify or improve at least a portion of the layout with a physical electronic design implementation tool, rather than using a separate circuit verification tool, during physical implementation of the layout with the physical electronic design implementation tool, wherein

the one or more patterns correspond to post-routing layout objects in the layout;

generating one or more libraries of the one or more patterns, the one or more libraries to be used by a physical design implementation tool to implement the layout of an electronic design; and

storing the one or more libraries into a non-transitory computer readable medium.

17. The computer program product of claim 16, in which the one or more libraries comprise an exact library which comprises a set of patterns that will be exactly matched during analysis of the electronic design.

18. The computer program product of claim 16, in which the one or more libraries comprise an inexact library which comprises a set of patterns that does not have to be exactly matched during analysis of an electronic design.

19. The computer program product of claim 16, in which the process further comprises:

generating data for pattern extraction by using a retargeting technique.

20. The computer program product of claim 19, in which the action of generating the data comprises:

mimicking or recreating of an existing design flow for replicate a processing result or a simulation result of the existing design flow.