Method for forming a nitride semiconductor layer and method for separating the nitride semiconductor layer from the substrate

• US 8,647,901 B2
• Filed: 06/11/2008
• Issued: 02/11/2014
• Est. Priority Date: 08/31/2006
• Status: Expired due to Fees

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: Guo, Yih-Der, Lai, Chih-Ming, Tsay, Jenq-Dar, Liu, Po-Chun
• Primary Examiner(s): YEUNG LOPEZ, FEIFEI
• Application Number:
  US12/137,519
• Publication Number:
  US 20080272378A1
• Time in Patent Office: 2,071 Days
• Field of Search: 438/481
• US Class Current: 438/29
• CPC Class Codes: C30B 25/02 Epitaxial-layer growth
• CPC Class Codes: C30B 29/403 AIII-nitrides
• CPC Class Codes: H01L 21/0237 Materials
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/0265 Pendeoepitaxy
• CPC Class Codes: H01L 21/02664 Aftertreatments planarisation in general H01L21/304
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate

Abstract

There is provided a method of forming a nitride semiconductor layer, including the steps of firstly providing a substrate on which a patterned epitaxy layer with a pier structure is formed. A protective layer is then formed on the patterned epitaxy layer, exposing a top surface of the pier structure. Next, a nitride semiconductor layer is formed over the patterned epitaxy layer connected to the nitride semiconductor layer through the pier structure, wherein the nitride semiconductor layer, the pier structure, and the patterned epitaxy layer together form a space exposing a bottom surface of the nitride semiconductor layer. Thereafter, a weakening process is performed to remove a portion of the bottom surface of the nitride semiconductor layer and to weaken a connection point between the top surface of the pier structure and the nitride semiconductor layer. Finally, the substrate is separated from the nitride semiconductor layer through the connection point.

Claims

1. A method of forming a nitride semiconductor layer, comprising the following steps:

providing a substrate;

forming a patterned epitaxy layer on a top surface of the substrate, wherein the patterned epitaxy layer comprises a plurality of pier structures and the plurality of pier structures each has a bar-like cross-sectional profile so that a portion of the top surface of the substrate is exposed, wherein the substrate comprises a different material than in the pier structures

forming a protective layer on the patterned epitaxy layer to cover all sidewalls of the pier structures and the exposed portion of the top surface of the substrate, wherein the protective layer exposes a top surface of the plurality of pier structures;

forming a nitride semiconductor layer over the patterned epitaxy layer connected to the nitride semiconductor layer through the pier structure, wherein the nitride semiconductor layer, the pier structures, and the protective layer together form a space exposing a bottom surface of the nitride semiconductor layer;

using an electrolytic solution to remove a portion of the bottom surface of the nitride semiconductor layer and to weaken a connection point between the top surface of the plurality of pier structures and the nitride semiconductor layer; and

separating the nitride semiconductor layer from the substrate through the connection point.

2. The method of forming the nitride semiconductor layer according to claim 1, wherein the electrolytic solution comprises a potassium hydroxide (KOH) solution.

3. The method of forming the nitride semiconductor layer according to claim 2, wherein the weakening process further comprises performing an irradiating process to facilitate the weakening process.

4. The method of forming the nitride semiconductor layer according to claim 1, wherein the concentration of the electrolytic solution is approximately 0.5˜

15M.

5. The method of forming the nitride semiconductor layer according to claim 1, wherein the forming method of the nitride semiconductor layer comprising a hydride vapor-phase epitaxy method and a metal organic chemical vapor-phase epitaxy method.

6. The method of forming the nitride semiconductor layer according to claim 1, wherein the material of the substrate comprises silicon, silicon carbide, sapphire, arsenide, phosphide, zinc oxide (ZnO), and magnesium oxide.

7. A separating method, comprising:

providing a substrate having a nitride semiconductor layer disposed on a to surface thereof and connected thereto through a plurality of pier structures, wherein the plurality of pier structures each has a bar-like cross-sectional profile and a protective layer covers the top surface of the substrate uncovered by the pier structures and all sidewalls of the pier structures such that the nitride semiconductor layer, the pier structures, and the protective layer together form a space exposing a bottom surface of the nitride semiconductor layer;

wherein the protective layer is formed after the pier structure are formed, wherein the entire to surface of each pier structure contacts the nitride semiconductor layer, and wherein the substrate comprises a different material than in the pier structures

using an electrolytic solution within the space to remove a portion of the bottom surface of the nitride semiconductor layer and to weaken a connection point between a top surface of the pier structure and the nitride semiconductor layer; and

separating the nitride semiconductor layer from the substrate.

8. The method of claim 7, wherein the electrolytic solution comprises a potassium hydroxide (KOH) solution.

9. The method of claim 8, wherein an irradiating method is used to expeditiously remove a portion of the nitride semiconductor layer.

10. The method of claim 7, wherein the concentration of the electrolytic solution is approximately 0.5˜

15M.

11. The method of claim 7, wherein the forming method of the nitride semiconductor layer comprising a hydride vapor-phase epitaxy method and a metal organic chemical vapor-phase epitaxy method.

12. The method of claim 7, wherein the material of the substrate comprises silicon, silicon carbide, sapphire, arsenide, phosphide, zinc oxide (ZnO), and magnesium oxide.