Surface modification for handling wafer thinning process

• US 8,647,925 B2
• Filed: 06/03/2010
• Issued: 02/11/2014
• Est. Priority Date: 10/01/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chiou, Wen-Chih, Shue, Shau-Lin, Wu, Weng-Jin, Hung, Ju-Pin
• Primary Examiner(s): Wagner, Jenny L
• Application Number:
  US12/792,975
• Publication Number:
  US 20110081749A1
• Time in Patent Office: 1,349 Days
• Field of Search: 438/109
• US Class Current: 438/109
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/14181 On opposite sides of the body
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/81001 involving a temporary auxiliary member not forming part of the bonding apparatus
• CPC Class Codes: H01L 2224/81005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/81191 wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81193 wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor

Abstract

A wafer is provided with a through via extending a portion of a substrate, an interconnect structure electrically connecting the through via, and a polyimide layer formed on the interconnect structure. Surface modification of the polyimide layer is the formation of a thin dielectric film on the polyimide layer by coating, plasma treatment, chemical treatment, or deposition methods. The thin dielectric film is adhered strongly to the polyimide layer, which can reduce the adhesion between the wafer surface and an adhesive layer formed in subsequent carrier attaching process.

Claims

1. A method, comprising:

providing a semiconductor substrate having a first surface and a second surface;

forming a through via extending into the semiconductor substrate from the first surface toward the second surface;

forming a first interconnect structure overlying the first surface of the semiconductor substrate and being electrically connected to the through via;

forming a dielectric buffer layer overlying the first interconnect structure;

forming a dielectric film on the dielectric buffer layer; and

attaching a carrier to the dielectric film of the semiconductor substrate by using an adhesive layer sandwiched between the carrier and the dielectric film.

2. The method of claim 1, wherein the dielectric buffer layer comprises a polymer layer.

3. The method of claim 1, wherein the dielectric buffer layer comprises a polyimide layer.

4. The method of claim 1, wherein the dielectric film comprises a silicon oxide layer.

5. The method of claim 1, wherein the dielectric film comprises a silicon nitride layer.

6. The method of claim 1, further comprising forming a bump structure overlying the dielectric buffer layer, wherein the dielectric film is formed on a surface of the bump structure.

7. The method of claim 1, further comprising performing a thinning process on the second surface of the semiconductor substrate to expose the through via.

8. The method of claim 7, further comprising forming a second interconnect structure overlying the second surface of the semiconductor substrate and being electrically connected the through via after performing the thinning process.

9. The method of claim 8, further comprising bonding a die onto the second surface of the semiconductor substrate after forming the second interconnect structure.

10. The method of claim 9, further comprising removing the carrier from the semiconductor substrate.

11. The method of claim 10, further comprising removing the dielectric film from the dielectric buffer layer.

12. A method, comprising:

providing a wafer comprising a semiconductor substrate having a first surface and a second surface;

forming a through via extending into a portion of the semiconductor substrate from the first surface of the semiconductor substrate toward the second surface of the semiconductor substrate;

forming a first interconnect structure overlying the first surface of the semiconductor substrate and being electrically connected to the through via;

forming a polyimide layer overlying the first interconnect structure;

forming a bump structure over the first interconnect structure and protruding from the polyimide layer; and

forming a polyimide surface modification film deposited on and covering the polyimide layer and the bump structure.

13. The method of claim 12, further comprising attaching a carrier on the polyimide surface modification film of the semiconductor substrate by using the adhesive layer.

14. The method of claim 12, wherein forming a polyimide surface modification film comprises forming a dielectric film on the polyimide layer.

15. The method of claim 12, wherein forming a polyimide surface modification film comprises forming a dielectric film by coating, plasma treatment, chemical treatment, or deposition methods.

16. The method of claim 13, further comprising performing a thinning process on the second surface of the semiconductor substrate to expose the through via.

17. The method of claim 16, further comprising forming a second interconnect structure overlying the second surface of the semiconductor substrate and being electrically connected to the through via after performing the thinning process.

18. The method of claim 17, further comprising bonding a die onto the second surface of the semiconductor substrate after forming the second interconnect structure.

19. The method of claim 18, further comprising removing the carrier from the semiconductor substrate.

20. The method of claim 13, further comprising removing the carrier from the semiconductor substrate.