Deep depleted channel MOSFET with minimized dopant fluctuation and diffusion levels
First Claim
Patent Images
1. A method comprising:
- forming a dummy gate, on a substrate, between a pair of spacers;
forming, in the substrate, a source and drain separated by a ground plane layer;
removing the dummy gate from the substrate, forming a cavity between the pair of spacers;
forming, after removal of the dummy gate, a channel layer on the substrate;
forming a high-k layer on the channel layer and on side surfaces of the cavity; and
forming a replacement gate in the cavity.
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Abstract
CMOS devices are fabricated with a channel layer having minimized dopant fluctuation and diffusion. Embodiments include forming a dummy gate, on a substrate, between a pair of spacers, forming, in the substrate, a source and drain separated by a ground plane layer, removing the dummy gate from the substrate, forming a cavity between the pair of spacers, forming, after removal of the dummy gate, a channel layer on the substrate, forming a high-k layer on the channel layer and on side surfaces of the cavity, and forming a replacement gate in the cavity.
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Citations
12 Claims
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1. A method comprising:
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forming a dummy gate, on a substrate, between a pair of spacers; forming, in the substrate, a source and drain separated by a ground plane layer; removing the dummy gate from the substrate, forming a cavity between the pair of spacers; forming, after removal of the dummy gate, a channel layer on the substrate; forming a high-k layer on the channel layer and on side surfaces of the cavity; and forming a replacement gate in the cavity. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method comprising:
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forming a dummy gate, on a substrate, between a pair of spacers; forming, in the substrate, a source and drain separated by a ground plane layer having a thickness of between 10 nanometers (nm) and 100 nm; forming, on the substrate, a depleted layer of silicon germanium (SiGe), silicon carbon (Si;
C), silicon germanium tin (SiGeSn), germanium tin (GeSn), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphorus (InP) to a thickness of between 3 nm and 30 nm, the depleted layer being formed of a different material than the source, the drain, the substrate, or a combination thereof;removing the dummy gate from the substrate, forming a cavity between the pair of spacers; epitaxially growing, after removal of the dummy gate, a channel layer on the ground plane layer, of intrinsic silicon (Si), intrinsic SiGe, or intrinsic germanium (Ge) to a thickness of between 3 nm and 30 nm; forming a high-k layer on the channel layer and on side surfaces of the cavity; and forming a replacement gate in the cavity. - View Dependent Claims (11, 12)
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Specification