Wafer level packaging bond

• US 8,647,962 B2
• Filed: 03/23/2010
• Issued: 02/11/2014
• Est. Priority Date: 03/23/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liu, Martin, Chu, Richard, Huang, Hsin-Ting, Peng, Jung-Huei, Hsieh, Yuan-Chih, Chao, Lan-Lin, Cheng, Chun-Wen, Tsai, Chia-Shiung, Lin, Hung Hua
• Primary Examiner(s): Luu, Chuong A.
• Application Number:
  US12/729,911
• Publication Number:
  US 20110233621A1
• Time in Patent Office: 1,421 Days
• Field of Search: 438/455, 438/696, 438/406, 438/51, 438/118, 438/119, 438/459
• US Class Current: 438/455
• CPC Class Codes: B81B 2207/012 the micromechanical device and the control or processing electronics being separate parts in the same package
• CPC Class Codes: B81C 1/00269 Bonding of solid lids or wafers to the substrate
• CPC Class Codes: B81C 2203/0118 Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
• CPC Class Codes: B81C 2203/035 Soldering
• CPC Class Codes: H01L 21/187 by direct bonding
• CPC Class Codes: H01L 25/162 the devices being mounted on two or more different substrates
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present disclosure provides a method of bonding a plurality of substrates. In an embodiment, a first substrate includes a first bonding layer. The second substrate includes a second bonding layer. The first bonding layer includes silicon; the second bonding layer includes aluminum. The first substrate and the second substrate are bonded forming a bond region having an interface between the first bonding layer and the second bonding layer. A device having a bonding region between substrates is also provided. The bonding region includes an interface between a layer including silicon and a layer including aluminum.

Claims

1. A method, comprising:

forming a first semiconductor device on a first substrate;

forming a first layer on the first substrate, wherein the first layer is amorphous silicon;

forming a second semiconductor device on a second substrate;

forming a second layer on the second substrate, wherein the second layer is aluminum; and

bonding the first layer and the second layer to create an interface between amorphous silicon and aluminum, wherein the interface provides an electrical connection between the first substrate and the second substrate.

2. The method of claim 1, wherein the forming the first layer includes doping the first layer.

3. The method of claim 1, wherein the forming the first layer includes a depositing amorphous silicon by a deposition process selected from the group consisting of physical vapor deposition (PVD), chemical vapor deposition (CVD), evaporation, electron beam evaporation (E-Gun), ion beam, energy beam, and combinations thereof.

4. The method of claim 1, wherein at least one of the forming the first semiconductor device and the forming the second semiconductor device includes forming a MEMS device.

5. The method of claim 1, wherein at least one of the forming the first semiconductor device and the forming the second semiconductor device includes using a complementary metal-oxide semiconductor (CMOS) process.

6. The method of claim 1, further comprising:

performing at least one of a wet etch and a dry etch on the first layer and the second layer prior to the bonding.

7. A method of fabricating a semiconductor device, comprising:

forming a micro-electro-mechanical systems (MEMS) device, disposed on a first substrate;

forming an integrated circuit disposed on a second substrate; and

bonding the first substrate and the second substrate, wherein the bond includes a first interface between a first bonding layer of amorphous silicon and a second bonding layer including aluminum, wherein the MEMS device and the integrated circuit are electrically connected by the first interface, and wherein the bonding the first interface provides an edge of a hermetically sealed cavity.

8. The method of claim 7, wherein the bonding includes a second interface between the first bonding layer and the second bonding layer, wherein no electrical connection is provided by the second interface, and wherein the second interface provides a second edge of the hermetically sealed cavity.

9. The method of claim 7, further comprising:

forming a second MEMS device on the second substrate.

10. The method of claim 7, wherein the bonding is performed at a temperature of approximately 50 Celsius.

11. A method, comprising:

providing a first substrate including a first bonding layer, wherein the first bonding layer is amorphous silicon;

providing a second substrate including a second bonding layer, wherein the second bonding layer is aluminum, and wherein the second bonding layer is one layer of a multi-layer interconnect (MLI) of an integrated circuit; and

bonding the first substrate and the second substrate, wherein the bonding includes forming a bond region having an interface between the amorphous silicon of the first bonding layer and the aluminum of the second bonding layer.

12. The method of claim 11, further comprising:

forming a micro-electro-mechanical systems (MEMS) device on at least one of the first substrate and the second substrate.

13. The method of claim 11, wherein the bond between the first bonding layer and the second bonding layer provides an electrical connection between the first substrate and the second substrate.