Buffer layer to enhance photo and/or laser sintering

• US 8,647,979 B2
• Filed: 03/26/2010
• Issued: 02/11/2014
• Est. Priority Date: 03/27/2009
• Status: Active Grant

• Current Assignee: Applied Nanotech, Inc. (Nano Magic, Inc.)
• Original Assignee: Ishihara Chemical Co., Ltd., Applied Nanotech Holdings Incorporated (Nano Magic, Inc.)
• Inventors: Yaniv, Zvi, Yang, Mohshi, Laxton, Peter B.
• Primary Examiner(s): ARMAND, MARC ANTHONY
• Application Number:
  US13/260,893
• Publication Number:
  US 20120049384A1
• Time in Patent Office: 1,418 Days
• Field of Search: 257/774, 257E27113-E27116, 257/23.018, 438/637, 438/151
• US Class Current: 438/637
• CPC Class Codes: B22F 1/054 Nanosized particles
• CPC Class Codes: B22F 2998/00 Supplementary information concerning processes or compositions relating to powder metallurgy
• CPC Class Codes: B22F 3/105 by using electric current other than for infrared radiant energy, laser radiation or plasma B22F3/11 takes precedence; by ultrasonic bonding B22F3/115 takes precedence
• CPC Class Codes: B22F 7/04 with one or more layers not made from powder, e.g. made from solid metal
• CPC Class Codes: B23K 2101/36 Electric or electronic devices
• CPC Class Codes: B23K 2103/50 Inorganic material, e.g. metals, not provided for in B23K2103/02 – B23K2103/26
• CPC Class Codes: B23K 2103/52 Ceramics
• CPC Class Codes: B23K 26/32 taking account of the properties of the material involved
• CPC Class Codes: B23K 26/34 Laser welding for purposes other than joining
• CPC Class Codes: B23K 35/0244 Powders, particles or spheres; Preforms made therefrom
• CPC Class Codes: H01L 21/268 using electromagnetic radiation, e.g. laser radiation
• CPC Class Codes: H01L 21/288 from a liquid, e.g. electrolytic deposition
• CPC Class Codes: H01L 21/4867 Applying pastes or inks, e.g. screen printing H01L21/486 takes precedence
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H05K 1/0201 Thermal arrangements, e.g. for cooling, heating or preventing overheating
• CPC Class Codes: H05K 1/092 Dispersed materials, e.g. conductive pastes or inks
• CPC Class Codes: H05K 2201/062 Means for thermal insulation, e.g. for protection of parts
• CPC Class Codes: H05K 2203/107 Using laser light
• CPC Class Codes: H05K 3/10 : in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
• CPC Class Codes: H05K 3/125 : by ink-jet printing
• CPC Class Codes: H05K 3/1283 : After-treatment of the printed patterns, e.g. sintering or curing methods
• CPC Class Codes: H05K 3/4664 : Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders H05K3/4647 takes precedence
• CPC Class Codes: Y10T 29/49156 : with selective destruction of conductive paths

Abstract

Conductive lines are deposited on a substrate to produce traces for conducting electricity between electronic components. A patterned metal layer is formed on the substrate, and then a layer of material having a low thermal conductivity is coated over the patterned metal layer and the substrate. Vias are formed through the layer of material having the low thermal conductivity thereby exposing portions of the patterned metal layer. A film of conductive ink is then coated over the layer of material having the low thermal conductivity and into the vias to thereby coat the portions of the patterned metal layer, and then sintered. The film of conductive ink coated over the portion of the patterned metal layer does not absorb as much energy from the sintering as the film of conductive ink coated over the layer of material having the low thermal conductivity. The layer of material having the low thermal conductivity may be a polymer, such as polyimide.

Claims

1. A method for depositing conductive lines on a substrate comprising:

depositing a metal layer in a pattern on the substrate;

coating a layer of material having a low thermal conductivity over the pattern metal layer and the substrate;

depositing a film of conductive ink over the layer of material having the low thermal conductivity; and

sintering the film of conductive ink.

2. The method as recited in claim 1, further comprising:

forming a via through the layer of material having the low thermal conductivity thereby exposing a portion of the patterned metal layer, wherein the depositing of the film of conductive ink includes depositing the film of conductive ink into the via to thereby coat the portion of the patterned metal layer with the film of conductive ink, wherein the film of conductive ink coating the portion of the patterned metal layer is also sintered.

3. The method as recited in claim 1, wherein the substrate has a thermal conductivity greater than the layer of material having the low thermal conductivity.

4. The method as recited in claim 2, wherein the film of conductive ink coated over the portion of the patterned metal layer does not dissipate as much energy from the sintering as the film of conductive ink coated over the layer of material having the low thermal conductivity.

5. The method as recited in claim 4, wherein the layer of material having the low thermal conductivity comprises a polymer.

6. The method as recited in claim 4, wherein the layer of material having the low thermal conductivity comprises polyimide.

7. The method as recited in claim 6, wherein the polyimide has a thickness of at least 50 microns.

8. The method as recited in claim 6, wherein the sintering is performed with a photo sintering apparatus.

9. The method as recited in claim 6, wherein the sintering is performed with a laser sintering apparatus.

10. The method as recited in claim 6, wherein the polyimide has a thickness of at least 5 microns.

11. The method as recited in claim 6, wherein the polyimide has a thickness of at least 2.3 microns.

12. The method as recited in claim 6, wherein the substrate comprises silicon.

13. The method as recited in claim 6, wherein the substrate comprises ceramic.

14. The method as recited in claim 6, wherein the film of conductive ink comprises copper nanoparticles.

15. The method as recited in claim 9, wherein the laser sintering apparatus comprises a solid state diode with an 830 nm wavelength and 800 mW power.

16. The method as recited in claim 15, wherein the solid state diode has a focus beam size of 15 microns in diameter.

17. Electronic circuitry comprising:

a substrate;

a pattern of metal traces deposited on the substrate;

a layer low thermal conductive material coated over the substrate and the pattern of metal traces deposited on the substrate, wherein vias are formed through the layer of low thermal conductive material over portions of the pattern of metal traces; and

a film of sintered conductive ink coated over the layer of low thermal conductive material coated over the substrate, wherein the film of sintered conductive ink is coated over the portions of the pattern of metal traces within the vias formed through the layer of low thermal conductive material.

18. The electronic circuitry as recited in claim 17, wherein the substrate has a thermal conductivity greater than the layer of low thermal conductive material.

19. The electronic circuitry as recited in claim 18, wherein the layer of low thermal conductive material comprises polyimide.

20. The electronic circuitry as recited in claim 19, wherein the polyimide has a thickness of at least 50 microns.

21. The electronic circuitry as recited in claim 19, wherein the sintered conductive ink comprises sintered copper nanoparticles sintered with a photo sintering apparatus.

22. The electronic circuitry as recited in claim 19, wherein the sintered conductive ink comprises sintered copper nanoparticles sintered with a laser sintering apparatus.

23. The electronic circuitry as recited in claim 19, wherein the polyimide has a thickness of at least 5 microns.

24. The electronic circuitry as recited in claim 19, wherein the polyimide has a thickness of at least 2.3 microns.

25. The electronic circuitry as recited in claim 19, wherein the substrate comprises silicon.