Light emitting diode (LED) using three-dimensional gallium nitride (GaN) pillar structures with planar surfaces

• US 8,648,328 B2
• Filed: 02/06/2012
• Issued: 02/11/2014
• Est. Priority Date: 12/27/2011
• Status: Active Grant

• Current Assignee: Elux Inc.
• Original Assignee: Sharp Laboratories of America Incorporated (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Crowder, Mark Albert, Zhan, Changqing, Schuele, Paul J.
• Primary Examiner(s): Jackson, Jr., Jerome
• Assistant Examiner(s): Fan, Bo
• Application Number:
  US13/367,120
• Publication Number:
  US 20130161584A1
• Time in Patent Office: 736 Days
• Field of Search: 257/99, 257/76, 257/9, 257/88, 257/79, 257/351, 257/292, 257/13, 257/627, 204/622, 438/479, 438/503, 438/27, 372/50.1, 298/72, 428/172, 428/142
• US Class Current: 257/9
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/49107 on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/95085 being a liquid, e.g. for fluidic self-assembly
• CPC Class Codes: H01L 2224/95136 involving guiding structures, e.g. shape matching, spacers or supporting members
• CPC Class Codes: H01L 24/95 at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
• CPC Class Codes: H01L 25/0753 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/10156 at the periphery
• CPC Class Codes: H01L 2924/12041 LED
• CPC Class Codes: H01L 2933/0008 Processes
• CPC Class Codes: H01L 2933/0016 relating to electrodes
• CPC Class Codes: H01L 2933/0033 relating to semiconductor body packages
• CPC Class Codes: H01L 33/005 Processes
• CPC Class Codes: H01L 33/0075 comprising nitride compounds
• CPC Class Codes: H01L 33/0095 Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
• CPC Class Codes: H01L 33/04 with a quantum effect structure or superlattice, e.g. tunnel junction
• CPC Class Codes: H01L 33/06 within the light emitting region, e.g. quantum confinement structure or tunnel barrier
• CPC Class Codes: H01L 33/08 with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body H01L27/15 takes precedence
• CPC Class Codes: H01L 33/18 within the light emitting region
• CPC Class Codes: H01L 33/24 of the light emitting region, e.g. non-planar junction
• CPC Class Codes: H01L 33/32 : containing nitrogen
• CPC Class Codes: H01L 33/42 : Transparent materials

Abstract

A method is provided for fabricating a light emitting diode (LED) using three-dimensional gallium nitride (GaN) pillar structures with planar surfaces. The method forms a plurality of GaN pillar structures, each with an n-doped GaN (n-GaN) pillar and planar sidewalls perpendicular to the c-plane, formed in either an m-plane or a-plane family. A multiple quantum well (MQW) layer is formed overlying the n-GaN pillar sidewalls, and a layer of p-doped GaN (p-GaN) is formed overlying the MQW layer. The plurality of GaN pillar structures are deposited on a first substrate, with the n-doped GaN pillar sidewalls aligned parallel to a top surface of the first substrate. A first end of each GaN pillar structure is connected to a first metal layer. The second end of each GaN pillar structure is etched to expose the n-GaN pillar second end and connected to a second metal layer.

Claims

1. A method for fabricating a light emitting diode (LED) using three-dimensional gallium nitride (GaN) pillar structures with planar surfaces, the method comprising;

forming a plurality of GaN pillar structures, each GaN pillar structure being formed as follows;

growing an n-doped GaN film overlying a second substrate;

generating a pattern of dislocation defects in a top surface of the GaN film;

wet etching the dislocation defects in the GaN film top surface;

removing GaN material damaged in response to forming the dislocation defects;

stopping the removal of GaN material in response to encountering c-planes, m-planes, and a-planes in the GaN film;

forming an n-doped GaN (n-GaN) pillar core having a first end attached to the second substrate, a second end, with at least one of the ends formed in a c-plane, and planar sidewalls perpendicular to the c-plane, formed in a plane selected from a group consisting of an m-plane and a-plane family;

forming a multiple quantum well (MQW) shell surrounding the n-GaN pillar sidewalls;

forming a p-doped GaN (p-GaN) shell surrounding the MQW shell;

detaching a plurality of GaN pillar structures from the second substrate;

depositing the plurality of GaN pillar structures on a first substrate, with the n-doped GaN pillar sidewalls aligned parallel to a top surface of the first substrate;

connecting a first end of each GaN pillar structure to a first metal layer to form a first electrode;

etching a second end of each GaN pillar structure to expose the n-GaN pillar second end; and

,

subsequent to etching the second end of each GaN pillar structure, connecting the second end of each GaN pillar structure to a second metal layer to form a second electrode.

2. The method of claim 1 wherein forming the MQW shell surrounding the n-GaN pillar core sidewalls, and the p-GaN shell surrounding the MQW shell includes forming the MQW shell surrounding the n-GaN pillar core sidewalls, and the p-GaN shell surrounding the MQW shell layer prior to detaching the first end of each GaN pillar core from the second substrate.

3. The method of claim 1 wherein forming the n-doped GaN pillar cores includes forming pillar cores having a shape selected from a group consisting of hexagonal and triangular.

4. The method of claim 1 further comprising:

providing the first substrate top surface with a plurality of first electrode digits and a plurality of opposing second electrode digits;

wherein depositing the plurality of GaN pillar structures on the first substrate includes;

suspending the GaN pillar structures in an ink solution;

flowing the ink solution over the first substrate top surface;

creating an alternating current (AC) electric field with a first field strength between each first electrode digit and corresponding second electrode digit; and

,

in response to the electric field, bridging a gap between each first electrode digit and corresponding second electrode digit with a GaN pillar structure.

5. The method of claim 4 wherein depositing the plurality of GaN pillar structures includes:

subsequent to bridging the gap between first and second electrode digits with the GaN pillar structure, increasing the electric field strength to capture the GaN pillar structures;

flowing a solvent over the first substrate top surface; and

,

in response to the solvent flow, removing GaN pillar structures not captured by the electric field.

6. The method of claim 5 wherein connecting the first end of each GaN pillar structure to a first metal layer includes:

conformally depositing a Ni layer overlying the first substrate top surface and GaN pillar structures; and

,

conformally depositing a transparent conductor overlying the Ni layer.

7. The method of claim 6 wherein etching the second end of each GaN pillar structure to expose the n-GaN second end includes, prior to etching the second end of each GaN pillar structure, etching to remove the transparent conductor and Ni layers overlying the second end of each GaN pillar structure;

and,

wherein connecting the second end of each GaN pillar structure to the second metal layer includes forming a metal interconnect layer interposed between the exposed n-GaN and the second metal layer.

8. A method for fabricating a light emitting diode (LED) using three-dimensional gallium nitride (GaN) pillar structures with planar surfaces, the method comprising:

forming a plurality of GaN pillar structures as follows;

growing an n-doped GaN film overlying a second substrate;

using a laser ablation process to induce thermal decomposition in a top surface of the GaN film;

in response to the thermal decomposition, forming cavities in the GaN film top surface;

wet etching the cavities in the GaN film top surface;

forming an n-doped GaN (n-GaN) pillar core having a first end attached to the second substrate, a second end, with at least one of the ends formed in a c-plane, and planar sidewalls perpendicular to the c-plane, formed in a plane selected from a group consisting of an m-plane and a-plane family;

forming a multiple quantum well (MQW) shell surrounding the n-GaN pillar sidewalls;

forming a p-doped GaN (p-GaN) shell surrounding the MQW shell;

detaching a plurality of GaN pillar structures from the second substrate;

depositing the plurality of GaN pillar structures on a first bstrate, with the n-doped GaN pillar sidewalls aligned parallel to a top surface of the first substrate;

connecting a first end of each GaN pillar structure to a first metal layer to form a first electrode;

etching a second end of each GaN pillar structure to expose the n-GaN pillar second end; and

,

subsequent to etching the second end of each GaN pillar structure, connecting the second end of each GaN pillar structure to a second metal layer to form a second electrode.

9. The method of claim 8 wherein forming the MQW shell surrounding the n-GaN pillar core sidewalls, and the p-GaN shell surrounding the MQW shell includes forming the MQW shell surrounding the n-GaN pillar core sidewalls, and the p-GaN shell surrounding the MQW shell layer prior to detaching the first end of each GaN pillar core from the second substrate.

10. The method of claim 8 wherein forming the n-doped GaN pillar cores includes forming pillar cores having a shape selected from a group consisting of hexagonal and triangular.

11. The method of claim 8 further comprising;

providing the first substrate top surface with a plurality of first electrode digits and a plurality of opposing second electrode digits;

wherein depositing the plurality of GaN pillar structures on the first substrate includes;

suspending the GaN pillar structures in an ink solution;

flowing the ink solution over the first substrate top surface;

creating an alternating current (AC) electric field with a first field strength between each first electrode digit and corresponding second electrode digit; and

,

in response to the electric field, bridging a gap between each first electrode digit and corresponding second electrode digit with a GaN pillar structure,

12. The method of claim 11 wherein depositing the plurality of GaN pillar structures includes:

subsequent to bridging the gap between first and second electrode digits with the GaN pillar structure, increasing the electric field strength to capture the GaN pillar structures;

flowing a solvent over the first substrate top surface; and

,

in response to the solvent flow, removing GaN pillar structures not captured by the electric field.

13. The method of claim 12 wherein connecting the first end of each GaN pillar structure to a first metal layer includes:

conformally depositing a Ni layer overlying the first substrate top surface and GaN pillar structures; and

,

conformally depositing a transparent conductor overlying the Ni layer.

14. The method of claim 13 wherein etching the second end of each GaN pillar structure to expose the n-GaN second end includes, prior to etching the second end of each GaN pillar structure, etching to remove the transparent conductor and Ni layers overlying the second end of each GaN pillar structure;

and,

wherein connecting the second end of each GaN pillar structure to the second metal layer includes forming a metal interconnect layer interposed between the exposed n-GaN and the second metal layer.