Semiconductor device, active matrix substrate and display device

• US 8,648,397 B2
• Filed: 11/02/2010
• Issued: 02/11/2014
• Est. Priority Date: 12/17/2009
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Kaneko, Seiji, Kitakado, Hidehito
• Primary Examiner(s): HOANG, QUOC DINH
• Application Number:
  US13/515,921
• Publication Number:
  US 20120256184A1
• Time in Patent Office: 1,197 Days
• Field of Search: 257/257, 257/258, 257/59, 257/72, 257252-254, 257/E33.072
• US Class Current: 257/257
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78633 with a light shield
• CPC Class Codes: H01L 29/78645 with multiple gate
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel

Abstract

A switching element (a semiconductor device) (18) having a top gate electrode (21) and a bottom gate electrode (23) is provided with a silicon layer (a semiconductor layer) (SL) that is arranged between the top gate electrode (21) and the bottom gate electrode (a light-shielding film) (23) and that has a source region (24), a drain region (28), a channel region (26), and low-concentration impurity regions (25, 27). Furthermore, the bottom gate electrode (23) is arranged so as to overlap the channel region (26), a part of the low-concentration impurity region (25), which is adjacent to the source region (24), and a part of the low-concentration impurity region (27), which is adjacent to the drain region (28). The bottom gate electrode (23) is controlled so as to have a prescribed potential.

Claims

1. A semiconductor device including a transistor, the transistor comprising:

a top gate electrode;

a bottom gate electrode;

a semiconductor layer disposed between said top gate electrode and said bottom electrode; and

a light-shielding film disposed below said bottom gate electrode,

wherein said bottom gate electrode is controlled to have a prescribed potential.

2. The semiconductor device according to claim 1, wherein, when said transistor is turned off, the potential of said bottom gate electrode is controlled such that accumulation occurs in a channel region of said semiconductor layer, and

wherein, when said transistor is turned on, the potential of the bottom gate electrode is controlled such that said channel region goes into inversion from depletion.

3. The semiconductor device according to claim 1, wherein a potential of said top gate electrode is controlled by a gate signal from a first signal wiring line that is connected to said top gate electrode, and

wherein the potential of said bottom gate electrode is controlled by capacitance coupling with said top gate electrode.

4. The semiconductor device according to claim 1, wherein a potential of said top gate electrode is controlled by a gate signal from a first signal wiring line that is connected to said top gate electrode, and

wherein the potential of said bottom gate electrode is controlled by a bottom gate signal from a second signal wiring line that is connected to said bottom gate electrode.

5. An active matrix substrate comprising the semiconductor device according to claim 1.

6. A display device comprising the semiconductor device according to claim 1.

7. The semiconductor device according to claim 1, wherein the semiconductor layer has a source region, a drain region, a channel region, and low-concentration impurity regions, and

wherein said bottom gate electrode is arranged so as to overlap said channel region, a part of said low-concentration impurity region, which is adjacent to said source region, and a part of said low-concentration impurity region, which is adjacent to said drain region.

8. The semiconductor device according to claim 7, wherein, in said semiconductor layer, said low-concentration impurity regions are formed so as to sandwich said channel region and so as to be offset from said top gate electrode.

9. A semiconductor device including a transistor, the transistor comprising:

a top gate electrode;

a bottom gate electrode;

a semiconductor layer disposed between said top gate electrode and said bottom electrode; and

a reflective electrode disposed above said top gate electrode,

wherein said bottom gate electrode is controlled to have a prescribed potential.

10. A semiconductor device including a transistor, the transistor comprising:

a top gate electrode;

a bottom gate electrode;

a semiconductor layer disposed between said top gate electrode and said bottom electrode; and

a reflective electrode disposed above said top gate electrode,

wherein said bottom gate electrode is controlled to have a prescribed potential.

11. The semiconductor device according to claim 10, wherein the semiconductor layer has a source region, a drain region, a channel region, and low-concentration impurity regions, and

wherein said bottom gate electrode is arranged so as to overlap said channel region, a part of said low-concentration impurity region, which is adjacent to said source region, and a part of said low-concentration impurity region, which is adjacent to said drain region.

12. The semiconductor device according to claim 11, wherein, in said semiconductor layer, said low-concentration impurity regions are formed so as to sandwich said channel region and so as to be offset from said top gate electrode.

13. The semiconductor device according to claim 10, wherein, when said transistor is turned off, the potential of said bottom gate electrode is controlled such that accumulation occurs in a channel region of said semiconductor layer, and

wherein, when said transistor is turned on, the potential of the bottom gate electrode is controlled such that said channel region goes into inversion from depletion.

14. The semiconductor device according to claim 10, wherein a potential of said top gate electrode is controlled by a gate signal from a first signal wiring line that is connected to said top gate electrode, and

wherein the potential of said bottom gate electrode is controlled by capacitance coupling with said top gate electrode.

15. The semiconductor device according to claim 10, wherein a potential of said top gate electrode is controlled by a gate signal from a first signal wiring line that is connected to said top gate electrode, and

wherein the potential of said bottom gate electrode is controlled by a bottom gate signal from a second signal wiring line that is connected to said bottom gate electrode.

16. An active matrix substrate comprising the semiconductor device according to claim 10.

17. A display device comprising the semiconductor device according to claim 10.