Electronic device and a transistor including a trench and a sidewall doped region

• US 8,648,398 B2
• Filed: 09/26/2012
• Issued: 02/11/2014
• Est. Priority Date: 12/10/2008
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Roig-Guitart, Jaume, Moens, Peter, Tack, Marnix
• Primary Examiner(s): YEUNG LOPEZ, FEIFEI
• Application Number:
  US13/627,287
• Publication Number:
  US 20130020637A1
• Time in Patent Office: 503 Days
• Field of Search: None
• US Class Current: 257/263
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors

Abstract

An electronic device can include a first layer having a primary surface, a well region lying adjacent to the primary surface, and a buried doped region spaced apart from the primary surface and the well region. The electronic device can also include a trench extending towards the buried doped region, wherein the trench has a sidewall, and a sidewall doped region along the sidewall of the trench, wherein the sidewall doped region extends to a depth deeper than the well region. The first layer and the buried region have a first conductivity type, and the well region has a second conductivity type opposite that of the first conductivity type. The electronic device can include a conductive structure within the trench, wherein the conductive structure is electrically connected to the buried doped region and is electrically insulated from the sidewall doped region. Processes for forming the electronic device are also described.

Claims

1. A transistor comprising:

a first layer having a primary surface;

a well region including a channel region of the transistor, wherein the channel region is adjacent to the primary surface;

a buried doped region spaced apart from the primary surface and underlying the well region, wherein the buried doped region includes a drain region of the transistor;

a gate electrode of the transistor disposed over the primary surface;

a trench extending towards the buried doped region, wherein the trench has a sidewall, and the trench is spaced apart from the channel region;

a sidewall doped region along the sidewall of the trench, wherein the sidewall doped region extends to a depth deeper than the well region, and wherein when viewed from the top, the sidewall doped region is below the well region; and

a conductive structure within the trench, wherein the conductive structure is electrically connected to the buried doped region and is electrically insulated from the sidewall doped region, wherein the conductive structure physically contacts either the buried doped region or a doped region located below the trench.

2. The transistor of claim 1, wherein:

the first layer and the buried doped region have a first conductivity type; and

the well region has a second conductivity type opposite that of the first conductivity type.

3. The transistor of claim 1, wherein substantially none of the gate electrode is disposed within the trench.

4. The transistor of claim 1, further comprising:

a well contact region lying adjacent to the primary surface and within the well region and having a higher peak doping concentration as compared to the well region; and

a source region of the transistor adjacent to the primary surface and within the well region and having a conductivity type opposite that of the well region and the well contact region.

5. The transistor of claim 4, wherein the conductive structure is closer to the source region than to the gate electrode.

6. The transistor of claim 1, wherein the transistor has an operating voltage of at least approximately 100 volts.

7. The transistor of claim 1, wherein the sidewall doped region has a substantially uniform doping concentration along the sidewall of the trench for a majority of the sidewall doped region, and a doping profile wherein a doping concentration of the sidewall doped region decreases with a distance from the sidewall of the trench.

8. The transistor of claim 1, wherein a combination of the well region and the sidewall doped region extends along a majority of the sidewall of the trench.

9. The transistor of claim 1, wherein the transistor is a VDMOS transistor.

10. An electronic device comprising:

a first layer having a primary surface;

a well region adjacent to the primary surface;

a buried doped region spaced apart from the primary surface and the well region;

a trench extending through the well region and towards the buried doped region, wherein from a cross-sectional view, the trench has a first sidewall and a second sidewall;

a first transistor including;

a channel region adjacent to the primary surface including a first portion of the well region, wherein the well region physically contacts a first sidewall surface of the trench;

a source region adjacent to the primary surface;

a gate electrode overlying the primary surface of the first layer; and

a first sidewall doped region along the first sidewall of the trench, wherein the first sidewall doped region extends below the first portion of the well region;

a second transistor including;

a second portion of the well region that lies adjacent to a second sidewall surface of the trench, wherein from a cross-sectional view, the first sidewall surface is opposite the second sidewall surface;

a source region adjacent to the primary surface; and

a gate electrode overlying the primary surface of the first layer;

a second sidewall doped region along a second sidewall of the trench, wherein the second sidewall doped region extends below the second portion of the well region; and

a conductive structure within the trench, wherein the conductive structure is electrically connected to the first and second transistors and is electrically insulated from the sidewall doped region wherein the conductive structure physically contacts either the buried doped region or a doped region located below the trench.

11. The electronic device of claim 10, wherein each of the first and second transistors is a VDMOS transistor.

12. The electronic device of claim 10, wherein each of the source regions of the first and second transistor is spaced apart from the trench.

13. The electronic device of claim 10, wherein:

a channel region of the first transistor includes a part of the first portion of the well region lying along the primary surface; and

a channel region of the second transistor includes a part of the second portion of the well region lying along the primary surface.

14. The electronic device of claim 13, wherein the channel regions of the first and second transistors are spaced apart from the trench.

15. The electronic device of claim 10, wherein the sidewall doped region is formed at a dose in a range of approximately 1×

10¹² ions/cm² or approximately 1×

10¹³ ions/cm².

16. The electronic device of claim 10, wherein:

the first sidewall doped region is immediately adjacent to the first portion of the well region and to a heavily doped region at a bottom of the trench; and

the second sidewall doped region is immediately adjacent to the second portion of the well region and spaced apart from the buried doped region.

17. The electronic device of claim 10, wherein the buried doped region is a common drain region for the first and second transistors.

18. The electronic device of claim 10, wherein substantially none of the gate electrodes of the first and second transistors are disposed in the trench.

19. The electronic device of claim 10, an insulating layer is disposed between the conductive structure and each of the first and second sidewall doped regions.

20. A transistor comprising:

a first layer having a primary surface;

a well region including a channel region of the transistor, wherein the channel region is adjacent to the primary surface;

a buried doped region spaced apart from the primary surface and underlying the well region, wherein the buried doped region includes a drain region of the transistor;

a gate electrode of the transistor disposed over the primary surface;

a trench extending through the well region towards the buried doped region, wherein the trench has a sidewall, and the trench is spaced apart from the channel region;

a sidewall doped region along the sidewall of the trench, wherein the sidewall doped region extends to a depth deeper than the well region; and

a conductive structure within the trench, wherein the conductive structure is electrically connected to the buried doped region and is electrically insulated from the sidewall doped region wherein the conductive structure physically contacts either the buried doped region or a doped region located below the trench.