Single poly EEPROM having a tunnel oxide layer

• US 8,648,406 B2
• Filed: 05/03/2012
• Issued: 02/11/2014
• Est. Priority Date: 12/29/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Dongbu HiTek Co., Ltd.
• Inventors: KIM, Hangeon
• Primary Examiner(s): Soward, Ida M
• Application Number:
  US13/463,268
• Publication Number:
  US 20130168755A1
• Time in Patent Office: 649 Days
• Field of Search: 257/317, 257/321, 257/E29.042
• US Class Current: 257/321
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
• CPC Class Codes: G11C 2216/10 Floating gate memory cells with a single polysilicon layer
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/7884 charging by hot carrier injection
• CPC Class Codes: H10B 41/60 the control gate being a doped region, e.g. single-poly memory cell

Abstract

A single poly EEPROM (Electrically Erasable Programmable Read Only Memory), which may include at least one of the following: (1) A second conductive type well formed on and/or over a semiconductor substrate. (2) A first conductive type source and drain regions formed in the second conductive type well. The single poly EEPROM may include at least one of: (a) A tunnel oxide layer formed on and/or over the second conductive type well. (b) A floating gate formed on and/or over the tunnel oxide layer and doped with second conductive type impurity ions. (c) A first conductive type impurity region formed in the second conductive type well adjacent to the floating gate. The floating gate may be configured such that a concentration of a region of the floating gate adjacent to the drain region is higher than that of the other region of the floating gate adjacent to the impurity region.

Claims

1. A single poly EEPROM (Electrically Erasable Programmable Read Only Memory), comprising:

a second conductive type well formed over a semiconductor substrate;

first conductive type source and drain regions formed in the second conductive type well;

a tunnel oxide layer formed over the second conductive type well;

a floating gate formed over the tunnel oxide layer and configured to be doped with second conductive type impurity ions; and

a first conductive type impurity region formed in the second conductive type well adjacent to the floating gate,

wherein the floating gate is configured such that a concentration of the second conductive type impurity ions in a first region of the floating gate adjacent to the drain region is higher than that of a second region of the floating gate adjacent to the first conductive type impurity region.

2. The single poly EEPROM of claim 1, wherein the floating gate such that a width of the first region of the floating gate adjacent to the drain region is greater than the width of the second region of the floating gate adjacent to the first conductive type impurity region.

3. The single poly EEPROM of claim 1, wherein the floating gate has a pattern in which a portion of the first region of the floating gate adjacent to the drain region is etched.

4. The single poly EEPROM of claim 1, wherein the floating gate has a pattern in which a portion of the first region of the floating gate adjacent to the drain region is patterned to have recesses.

5. The single poly EEPROM of claim 1, wherein the single poly EEPROM executes hot electron injection programming.

6. The single poly EEPROM of claim 1, wherein the tunnel oxide layer has a thickness of a first region of the tunnel oxide layer adjacent to the drain region is greater than that of a second region of the tunnel oxide layer adjacent to the first conductive type impurity region.

7. The single poly EEPROM of claim 1, wherein the first conductive type is a P type impurity and the second conductive type is an N type impurity.

8. The single poly EEPROM of claim 1, wherein the second conductive type well is formed on the semiconductor substrate.

9. The single poly EEPROM of claim 1, wherein the tunnel oxide layer is formed on the second conductive type well.

10. The single poly EEPROM of claim 1, wherein the floating gate is formed on the tunnel oxide layer.