ESD protection device and method

• US 8,648,419 B2
• Filed: 01/20/2010
• Issued: 02/11/2014
• Est. Priority Date: 01/20/2010
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Gendron, Amaury, Gill, Chai Ean, Hong, Changsoo
• Primary Examiner(s): Tran, Minh-Loan T
• Assistant Examiner(s): Erdem, Fazli
• Application Number:
  US12/690,771
• Publication Number:
  US 20110176244A1
• Time in Patent Office: 1,483 Days
• Field of Search: None
• US Class Current: 257/355
• CPC Class Codes: H01L 27/0259 using bipolar transistors as protective elements
• CPC Class Codes: H01L 29/0821 Collector regions of bipolar transistors
• CPC Class Codes: H01L 29/66234 Bipolar junction transistors [BJT]
• CPC Class Codes: H01L 29/6625 Lateral transistors H01L29/66242 and H01L29/66265 take precedence
• CPC Class Codes: H01L 29/735 Lateral transistors

Abstract

An electrostatic discharge (ESD) protection clamp (21, 21′, 70, 700) for protecting associated devices or circuits (24), comprises a bipolar transistors (21, 21′, 70, 700) in which doping of facing base (75) and collector (86) regions is arranged so that avalanche breakdown occurs preferentially within a portion (84, 85) of the base region (74, 75) of the device (70, 700) away from the overlying dielectric-semiconductor interface (791). Maximum variations (ΔVt1)_MAX of ESD triggering voltage Vt1 as a function of base-collector spacing dimensions D due, for example, to different azimuthal orientations of transistors (21, 21′, 70, 700) on a semiconductor die or wafer is much reduced. Triggering voltage consistency and manufacturing yield are improved.

Claims

1. An electronic assembly, comprising:

first and second external terminals;

a core circuit coupled between the first and second external terminals;

a bipolar transistor electrostatic discharge (ESD) clamp coupled between the first and second external terminals, wherein the bipolar transistor electrostatic discharge (ESD) clamp comprises;

an emitter region of a first doping density electrically coupled to the first terminal, a collector region of a second doping density electrically coupled to the second terminal, a base region of a third doping density located between the emitter region and the collector region, and a further region of a fourth doping density located between the base region and the collector region, wherein at least the further region extends to an overlying dielectric-semiconductor interface; and

wherein

the base region has a first dopant boundary with the further region and the collector region has a second dopant boundary with the further region and wherein at least one of the first and second dopant boundaries has a maximum dopant density at a distance Y>

0 beneath the dielectric-semiconductor interface.

2. The assembly of claim 1, wherein Y>

0.1 micrometers.

3. The assembly of claim 1, wherein the first and second dopant boundaries have maximum dopant concentrations at distances Y1 and Y2, respectively, beneath the dielectric-semiconductor interface, and wherein Y1>

0 and Y2>

0.

4. The assembly of claim 1, wherein the base region and the collector region are more heavily doped than the further region.

5. The assembly of claim 4, wherein a peak dopant concentration of the base region and a peak dopant concentration of the collector region exceed an average dopant concentration of the further region by at least a factor of 5.

6. The assembly of claim 5, wherein the peak dopant concentration of the base region and the peak dopant concentration of the collector region exceed the average dopant concentration of the further region by at least a factor of 10.

7. The assembly of claim 1, wherein the emitter region and a base contact region are substantially shorted together.

8. The assembly of claim 1, wherein the first and second dopant boundaries are separated by a minimum distance D through the further region, and wherein the minimum distance D occurs at a depth Y>

0 beneath the dielectric-semiconductor interface.

9. The assembly of claim 8, wherein the bipolar transistor electrostatic discharge (ESD) clamp is adapted to have an avalanche trigger voltage Vt1 substantially determined by D.

10. A bipolar transistor electrostatic discharge (ESD) clamp formed in a substrate having a first surface, and coupled to first and second terminals, and comprising:

an emitter coupled to the first terminal, a collector coupled to the second terminal, a base located between the emitter and the collector and an intermediate semiconductor portion coupled between the base and the collector and more lightly doped than the base and the collector;

wherein at least the intermediate semiconductor portion extends to a dielectric-semiconductor interface at or near the first surface; and

wherein the intermediate semiconductor portion has a first interface with the base and second interface with the collector extending away from the dielectric-semiconductor interface and wherein the first and second interfaces have a minimum separation D located a distance Y>

0 below the dielectric-semiconductor interface.

11. The ESD clamp of claim 10, wherein Y>

0.1 micrometers.

12. The ESD clamp of claim 10, further comprising a buried layer region underlying the base and Ohmically coupled to the collector.

13. The ESD clamp of claim 10, wherein the intermediate semiconductor portion is more lightly doped than the base and the collector by at least a factor of 5.

14. A bipolar transistor electrostatic discharge (ESD) clamp triggered by an avalanche breakdown occurring at a predetermined triggering voltage Vt1, the bipolar transistor ESD clamp comprising:

a collector region;

a base region laterally spaced from the collector region;

an intermediate semiconductor portion between the collector region and the base region; and

a body of dielectric material overlying the intermediate semiconductor portion and forming therewith a dielectric-semiconductor interface;

wherein the maximum doping density of the collector region and the maximum doping density of the base region are each located a predetermined distance beneath the dielectric-semiconductor interface such, when the triggering voltage Vt1 is applied to the bipolar ESD clamp, the avalanche breakdown occurs within a region of the intermediate semiconductor portion located at a depth Y>

0 beneath the dielectric-semiconductor interface.

15. The ESD clamp of claim 14, wherein Y>

0.1 micrometers.

16. The ESD clamp of claim 14, wherein the body of dielectric material comprises a shallow trench isolation feature formed in the intermediate semiconductor portion.

17. The ESD clamp of claim 14, wherein the intermediate semiconductor portion has a distance D defined by the lateral spacing between the collector and the base region, wherein D varies with increasing distance from the dielectric-semiconductor interface.

18. The ESD clamp of claim 14, wherein the collector region underlies the body of dielectric material.

19. The ESD clamp of claim 18, further comprising:

a WELL region adjacent the collector region, the body of dielectric material extending laterally from the base region to the WELL region; and

a buried layer region underlying the base region and ohmically coupled to the collector region by the WELL region.

20. The ESD clamp of claim 19, wherein the collector region, the semiconductor region, and the WELL region are each doped with a P-type dopant, and wherein the base region and the buried layer region are each doped with an N-type dopant.