Tunneling transistors

• US 8,648,426 B2
• Filed: 12/17/2010
• Issued: 02/11/2014
• Est. Priority Date: 12/17/2010
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Jin, Insik, Tian, Wei, Vaithyanathan, Venugopalan, Bedoya, Cedric, Siegert, Markus
• Primary Examiner(s): Karimy, Timor
• Application Number:
  US12/971,393
• Publication Number:
  US 20120153400A1
• Time in Patent Office: 1,152 Days
• Field of Search: 257/390, 257/411, 257/E27.099, 257/E29.255
• US Class Current: 257/390
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/66977 Quantum effect devices, e.g. using quantum reflection, diffraction or interference effects, i.e. Bragg- or Aharonov-Bohm effects
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A transistor including a source; a drain; a gate region, the gate region including a gate; an island; and a gate oxide, wherein the gate oxide is positioned between the gate and the island; and the gate and island are coactively coupled to each other; and a source barrier and a drain barrier, wherein the source barrier separates the source from the gate region and the drain barrier separates the drain from the gate region.

Claims

1. A transistor comprising:

a source;

a drain;

a gate region, the gate region comprising;

a gate;

an island; and

a gate oxide,

wherein the gate oxide is positioned between the gate and the island; and

the gate and island are electrically coactively coupled to each other; and

a source barrier and a drain barrier,

wherein the source barrier separates the source from the gate region and the drain barrier separates the drain from the gate region, and wherein the source barrier and drain barrier are thinner proximate the island than they are proximate the gate.

2. The transistor according to claim 1, wherein the source barrier and drain barrier have a variable thickness.

3. The transistor according to claim 1, wherein the source and drain comprise n- or p-type doped silicon.

4. The transistor according to claim 1, wherein the gate comprises a metal, a metal oxide or poly-silicon.

5. The transistor according to claim 1, wherein the gate oxide comprises SiO₂, or a material having a high dielectric constant.

6. The transistor according to claim 5, wherein the gate oxide comprises ZrO₂, Y₂O₃, HfO₂, SiO_xN_y, or solid solutions thereof.

7. The transistor according to claim 1, wherein the source barrier and drain barrier independently comprise SiO₂, or a material having a high dielectric constant.

8. The transistor according to claim 7, wherein the source barrier and drain barrier independently comprise ZrO₂, Y₂O₃, HfO₂, SiO_xN_y, or solid solutions thereof.

9. The transistor according to claim 1, wherein the island comprises n- or p-type doped silicon or a semiconductor oxide.

10. The transistor according to claim 9, wherein the island comprises SnO, Sn₂O₃, 1n₂O₃, or solid solutions thereof

11. The transistor according to claim 1, wherein the source, source barrier, island, drain barrier, and drain are stacked on a substrate.

12. The transistor according to claim 11, wherein the source barrier is thicker than the drain barrier.

13. The transistor according to claim 11, wherein at least the island of the gate region contacts both the source barrier and the drain barrier.

14. The transistor according to claim 13, wherein the gate contacts only the gate oxide.

15. A memory array comprising:

a first memory array layer that comprises a plurality of memory units, each memory unit comprising a transistor electrically coupled to a memory cell; and

a second memory array layer that comprises a plurality of memory units, each memory unit comprising a transistor electrically coupled to a memory cell,

wherein the transistors comprise;

a source;

a drain;

a gate region, the gate region comprising;

a gate;

an island; and

a gate oxide, wherein the gate oxide is positioned between the gate and the island; and

the gate and island are electrically coactively coupled to each other; and

a source barrier and a drain barrier,

wherein the source barrier separates the source from the gate region and the drain barrier separates the drain from the gate region; and

wherein the source barrier and drain barrier are thinner proximate the island than they are proximate the gate.

16. The memory array according to claim 15, wherein the first memory array layer and the second memory array layer includes a plurality of rows and columns of memory units.

17. The memory array according to claim 15 further comprising three or more memory array layers stacked sequentially to form the memory array.